IRC logs for #openrisc Saturday, 2014-09-20

--- Log opened Sat Sep 20 00:00:00 2014
stekernolofk: there are several ways I could get it to work, all which require (per SoC) additional work.05:27
stekernmy setup looks like this:
stekernthat will produce signals that are called wb_m2s_or1k0_i_xxx, wb_m2s_or1k1_i_xxx, wb_m2s_or1k2_i_xxx, wb_m2s_or1k3_i_xxx05:29
stekernbut I want one that is wb_m2s_or1k_i_xxx[0:3]05:29
stekernwhat would be really cool, would be if wb_intercon.conf could be like this to generate signals like that:
stekerndon't worry, I can take a look at implementing it, as long as you're on-board on the idea ;)05:33
mor1kx[mor1kx] bandvig pushed 1 new commit to withfpu:
mor1kxmor1kx/withfpu 31b71bd Andrey Bacherov: Change FPU's modules interface to verilog-2001 style. Replace tabs by whitespaces and remove unnecessary whitespaces from line ends.09:54
olofkstekern: Would that require sv2005 style 2d-arra ports?13:26
olofkBecause I'm not sure all tools support that yet13:27
olofkAnd what would the .conf entry look like?13:34
olofkACtually, thinking a bit more about it, I'm  a bit worried that it will increase the complexity with little gain13:38
olofkI think you should start with hacking on the generated verilog files locally in your system and we can take a lok at updating wb_intercon_gen after that13:39
olofkBut otoh it would be handy for other things too, like when you hae several spi or i2c slaves13:41
stekernolofk: what's complex about it? all you need to do is generate the wires in wb_intercon.vh as an array14:02
stekernand then connect the individual elements to the respective ports14:03
stekernI already gave you an example of how the .conf entry would look like14:03
stekernand you don't need any arrays at the module interfaces14:04
stekernolofk: like this:
PaulfraOSAAOk, so I added the uart16550 to the lx9_microboard project, it seems to include it and the top file has input uart_rx, output uart_tx in it, but I can't see where the pads connect to the component, should I manually edit the lx9_microbard_top.v file to instanitate the component?14:39
PaulfraOSAAShort question: when adding a component (e.g. a uart) should I add the component to the toplevel .v file or is there some kind of script-magic to take care of that part?15:02
PaulfraOSAAOh, and Opencores seems to still be down15:18
stekernPaulfraOSAA: you need to instantiate it manually at the top-level .v (i.e. there's no top-level autogeneration), but the wishbone interconnect signals are declared in wb_intercon.vh15:36
poke53282I wish I had an answer to this FPU benchmarking question.16:42
poke53282pov-ray benchmark maybe, but they use double for sure16:45
CodeWarCurious what kind of simulators we use for this project? Are these SystemC Approximately Timed model or LT or is it even SystemC?17:13
poke53282dalias: ltrace uses indeed only ptrace. But then it sets breakpoints and analyzes the plt table.17:40
poke53282So it should be independent of musl related features17:41
poke53282wrong chatroom17:45
poke53282does anyone has the openrisc architecture manual? is down17:47
poke53282I need information about l.trap17:51
stekernthe link from goes there too18:16
poke53282yes, I found it in the meantime18:18
PaulfraOSAAI have a question about the led_blink project. It seems to me only the top loop gets executed, there seems to be no jump to the l2 t2 labels?18:18
stekernPaulfraOSAA: which led blinker is that?18:20
stekernthe one here?
PaulfraOSAAThe asm sw in the lx9_microboard and the de1, so probably that one yeah18:22
PaulfraOSAAThanks for the link btw, that looks pretty much like just what I was looking for :)18:22
PaulfraOSAAOnly in the version I got, there is an unconditional branc to bl1 just before the nop in line 2218:23
stekernhmm, that wouldn't blink much then18:24
PaulfraOSAAonly... it does18:24
stekernmaybe there are other differences?18:26
PaulfraOSAAAhh, mine also sets every other led on and ror's it, so if the leds are connected to led(0) led( 2) led... then it would blink in the pattern I'm seeing18:29
PaulfraOSAAUnfortunately I don't see myself spending a lot of time learning Verilog, I have enough in keeping up with my VHDL. Maybe I should just swich to the zpu18:30
stekernwell, I don't see much difference in knowing verilog and VHDL, it's mostly about a mindset18:34
stekernbesides, zpu, does it have anything else going for it besides being small?18:44
poke53282stekern: Now I know why you like musl. I saw the porting effort. It's basically nothing and looks very easy.19:35
stekernyeah, I think most time I spent was to understand how TLS works and to get src/ldso/or1k/start.s right20:00
stekernand then iron out bugs made by silly mistakes20:01
stekernhaving support from dalias made the effort a lot easier too ;)20:02
PaulfraOSAAwhen the module is called uart_top I should instantiate the module with uart_top uart( .wb_clk_i ... right?20:21
stekernlike this:
PaulfraOSAAyay! I know Verilog XD20:25
stekernPaulfraOSAA: I told you, it's not hard to transfer from VHDL ;)20:35
stekernit might actually be slightly more difficult the other way around20:35
PaulfraOSAAAre the wb_m2s_[module]_[WBconnection] wires generated automagically, and how can I guess / find the names?20:37
stekernyes, they are generated and you can find them in wb_intercon.vh20:38
stekernit's not *automagically* generated though, you have to run a python script on the wb_intercon.conf file20:41
stekernsave this as a '' in the 'data' dir and run it:
stekernyou have to add the uart to the .conf file too20:43
PaulfraOSAAI've already added it to the .conf (that was the part I got), shouldn't the fusesoc build take care of it?20:54
stekernyes, it *should*, but it doesn't (yet)20:56
PaulfraOSAAby adding to the .conf file you mean the .core file right?20:58
stekernah, no. I mean the wb_intecon.conf file (as in the example that I linked to above)20:59
PaulfraOSAAyeah, it's in that file too20:59
PaulfraOSAASomebody should really do a post about what it takes to add a component to an existing design. On the other hand, there will be as soon as i figure it out :)21:00
PaulfraOSAAOk, now when I look in the .v file there are a lot of wb_m2s_or1200_d_uart0_xxx wb_m2s_dbg_uart0_xxx wb_m2s_resize_uart0_xxx and wb_uart0_xxx_[io] (the last one is not a wire but in- and outports)21:10
PaulfraOSAANone of the corresponding ones for e.g. the gpio feature in the toplevel.v file :(21:10
PaulfraOSAAalso, shouln't it be in the .vh file?21:11
* PaulfraOSAA is getting very confused21:11
stekernit should be (and is) in the .vh file21:13
stekernyou can ignore what's going on in the .v (if you're not really interested in what's happening in that)21:14
PaulfraOSAAdoes the wb_intercon_gen script also generate the .vh file?21:14
PaulfraOSAAAnd there it is, thank you very much, but you should really go for the path of least surprise :)21:15
PaulfraOSAAJust out of curiosity, is this documented anywhere? (even on the now defunct
PaulfraOSAATodoList: 1) document the progress 2) make pyQt gui tool to automate the process of adding components21:17
PaulfraOSAAWhat is the verilog equivalent for "open" ?22:24
PaulfraOSAA() ?22:25
PaulfraOSAAWell, it seemed to work...22:30
--- Log closed Sun Sep 21 00:00:02 2014

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