| --- Log opened Sat Sep 20 00:00:00 2014 | ||
| stekern | olofk: there are several ways I could get it to work, all which require (per SoC) additional work. | 05:27 |
|---|---|---|
| stekern | my setup looks like this: http://pastie.org/9578064 | 05:27 |
| stekern | that will produce signals that are called wb_m2s_or1k0_i_xxx, wb_m2s_or1k1_i_xxx, wb_m2s_or1k2_i_xxx, wb_m2s_or1k3_i_xxx | 05:29 |
| stekern | but I want one that is wb_m2s_or1k_i_xxx[0:3] | 05:29 |
| stekern | what would be really cool, would be if wb_intercon.conf could be like this to generate signals like that: http://pastie.org/9578072 | 05:32 |
| stekern | don't worry, I can take a look at implementing it, as long as you're on-board on the idea ;) | 05:33 |
| mor1kx | [mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/31b71bd37f9db87a7194072644f30f14485947df | 09:54 |
| mor1kx | mor1kx/withfpu 31b71bd Andrey Bacherov: Change FPU's modules interface to verilog-2001 style. Replace tabs by whitespaces and remove unnecessary whitespaces from line ends. | 09:54 |
| olofk | stekern: Would that require sv2005 style 2d-arra ports? | 13:26 |
| olofk | array | 13:26 |
| olofk | Because I'm not sure all tools support that yet | 13:27 |
| olofk | And what would the .conf entry look like? | 13:34 |
| olofk | ACtually, thinking a bit more about it, I'm a bit worried that it will increase the complexity with little gain | 13:38 |
| olofk | I think you should start with hacking on the generated verilog files locally in your system and we can take a lok at updating wb_intercon_gen after that | 13:39 |
| olofk | But otoh it would be handy for other things too, like when you hae several spi or i2c slaves | 13:41 |
| stekern | olofk: what's complex about it? all you need to do is generate the wires in wb_intercon.vh as an array | 14:02 |
| stekern | and then connect the individual elements to the respective ports | 14:03 |
| stekern | I already gave you an example of how the .conf entry would look like | 14:03 |
| stekern | and you don't need any arrays at the module interfaces | 14:04 |
| stekern | olofk: like this: http://pastie.org/9578973 | 14:17 |
| PaulfraOSAA | Ok, so I added the uart16550 to the lx9_microboard project, it seems to include it and the top file has input uart_rx, output uart_tx in it, but I can't see where the pads connect to the component, should I manually edit the lx9_microbard_top.v file to instanitate the component? | 14:39 |
| PaulfraOSAA | Short question: when adding a component (e.g. a uart) should I add the component to the toplevel .v file or is there some kind of script-magic to take care of that part? | 15:02 |
| PaulfraOSAA | Oh, and Opencores seems to still be down | 15:18 |
| stekern | PaulfraOSAA: you need to instantiate it manually at the top-level .v (i.e. there's no top-level autogeneration), but the wishbone interconnect signals are declared in wb_intercon.vh | 15:36 |
| poke53282 | I wish I had an answer to this FPU benchmarking question. | 16:42 |
| poke53282 | pov-ray benchmark maybe, but they use double for sure | 16:45 |
| CodeWar | Curious what kind of simulators we use for this project? Are these SystemC Approximately Timed model or LT or is it even SystemC? | 17:13 |
| poke53282 | dalias: ltrace uses indeed only ptrace. But then it sets breakpoints and analyzes the plt table. | 17:40 |
| poke53282 | So it should be independent of musl related features | 17:41 |
| poke53282 | wrong chatroom | 17:45 |
| poke53282 | :) | 17:45 |
| poke53282 | does anyone has the openrisc architecture manual? opencores.org is down | 17:47 |
| poke53282 | I need information about l.trap | 17:51 |
| stekern | poke53282: https://github.com/openrisc/doc | 18:15 |
| stekern | the link from opencores.org/or1k goes there too | 18:16 |
| poke53282 | yes, I found it in the meantime | 18:18 |
| PaulfraOSAA | I have a question about the led_blink project. It seems to me only the top loop gets executed, there seems to be no jump to the l2 t2 labels? | 18:18 |
| stekern | PaulfraOSAA: which led blinker is that? | 18:20 |
| stekern | the one here? http://www.elec4fun.fr/2011-03-30-10-16-30/2012-08-22-20-50-31/or1200-barebox-on-de1 | 18:21 |
| PaulfraOSAA | The asm sw in the lx9_microboard and the de1, so probably that one yeah | 18:22 |
| PaulfraOSAA | Thanks for the link btw, that looks pretty much like just what I was looking for :) | 18:22 |
| PaulfraOSAA | Only in the version I got, there is an unconditional branc to bl1 just before the nop in line 22 | 18:23 |
| stekern | hmm, that wouldn't blink much then | 18:24 |
| PaulfraOSAA | only... it does | 18:24 |
| stekern | maybe there are other differences? | 18:26 |
| PaulfraOSAA | Ahh, mine also sets every other led on and ror's it, so if the leds are connected to led(0) led( 2) led... then it would blink in the pattern I'm seeing | 18:29 |
| PaulfraOSAA | Unfortunately I don't see myself spending a lot of time learning Verilog, I have enough in keeping up with my VHDL. Maybe I should just swich to the zpu | 18:30 |
| stekern | well, I don't see much difference in knowing verilog and VHDL, it's mostly about a mindset | 18:34 |
| stekern | besides, zpu, does it have anything else going for it besides being small? | 18:44 |
| poke53282 | stekern: Now I know why you like musl. I saw the porting effort. It's basically nothing and looks very easy. | 19:35 |
| stekern | yeah, I think most time I spent was to understand how TLS works and to get src/ldso/or1k/start.s right | 20:00 |
| stekern | and then iron out bugs made by silly mistakes | 20:01 |
| stekern | having support from dalias made the effort a lot easier too ;) | 20:02 |
| PaulfraOSAA | when the module is called uart_top I should instantiate the module with uart_top uart( .wb_clk_i ... right? | 20:21 |
| stekern | yes | 20:23 |
| stekern | like this: https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/rtl/verilog/orpsoc_top.v#L590 | 20:23 |
| PaulfraOSAA | yay! I know Verilog XD | 20:25 |
| stekern | PaulfraOSAA: I told you, it's not hard to transfer from VHDL ;) | 20:35 |
| stekern | it might actually be slightly more difficult the other way around | 20:35 |
| PaulfraOSAA | Are the wb_m2s_[module]_[WBconnection] wires generated automagically, and how can I guess / find the names? | 20:37 |
| stekern | yes, they are generated and you can find them in wb_intercon.vh | 20:38 |
| stekern | it's not *automagically* generated though, you have to run a python script on the wb_intercon.conf file | 20:41 |
| stekern | save this as a 'wb_intercon_gen.sh' in the 'data' dir and run it: http://pastie.org/9579758 | 20:42 |
| stekern | you have to add the uart to the .conf file too | 20:43 |
| stekern | https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/data/wb_intercon.conf#L32-L35 | 20:44 |
| stekern | and https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/data/wb_intercon.conf#L11 | 20:44 |
| PaulfraOSAA | I've already added it to the .conf (that was the part I got), shouldn't the fusesoc build take care of it? | 20:54 |
| stekern | yes, it *should*, but it doesn't (yet) | 20:56 |
| PaulfraOSAA | by adding to the .conf file you mean the .core file right? | 20:58 |
| stekern | ah, no. I mean the wb_intecon.conf file (as in the example that I linked to above) | 20:59 |
| PaulfraOSAA | yeah, it's in that file too | 20:59 |
| PaulfraOSAA | Somebody should really do a post about what it takes to add a component to an existing design. On the other hand, there will be as soon as i figure it out :) | 21:00 |
| stekern | =P | 21:02 |
| PaulfraOSAA | Ok, now when I look in the .v file there are a lot of wb_m2s_or1200_d_uart0_xxx wb_m2s_dbg_uart0_xxx wb_m2s_resize_uart0_xxx and wb_uart0_xxx_[io] (the last one is not a wire but in- and outports) | 21:10 |
| PaulfraOSAA | None of the corresponding ones for e.g. the gpio feature in the toplevel.v file :( | 21:10 |
| PaulfraOSAA | also, shouln't it be in the .vh file? | 21:11 |
| * PaulfraOSAA is getting very confused | 21:11 | |
| stekern | it should be (and is) in the .vh file | 21:13 |
| stekern | you can ignore what's going on in the .v (if you're not really interested in what's happening in that) | 21:14 |
| PaulfraOSAA | does the wb_intercon_gen script also generate the .vh file? | 21:14 |
| stekern | yes | 21:14 |
| PaulfraOSAA | And there it is, thank you very much, but you should really go for the path of least surprise :) | 21:15 |
| PaulfraOSAA | Just out of curiosity, is this documented anywhere? (even on the now defunct opencores.org) | 21:16 |
| PaulfraOSAA | TodoList: 1) document the progress 2) make pyQt gui tool to automate the process of adding components | 21:17 |
| PaulfraOSAA | What is the verilog equivalent for "open" ? | 22:24 |
| PaulfraOSAA | () ? | 22:25 |
| PaulfraOSAA | :q | 22:26 |
| PaulfraOSAA | Well, it seemed to work... | 22:30 |
| --- Log closed Sun Sep 21 00:00:02 2014 | ||
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