IRC logs for #openrisc Sunday, 2014-09-14

--- Log opened Sun Sep 14 00:00:51 2014
-!- sb0_ is now known as sb002:32
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master a14d275 Florent Kermarrec: mor1kx_execute_alu: try some optimizations on logic operations06:38
mor1kxmor1kx/master 3eeca5d Stefan Kristiansson: follow-up on Florents logic optimization06:38
mor1kx[mor1kx] skristiansson force-pushed master from 3eeca5d to 4f9d080:
mor1kxmor1kx/master bba8660 Florent Kermarrec: mor1kx_execute_alu: logic operation optimizations...06:39
mor1kxmor1kx/master 4f9d080 Stefan Kristiansson: execute_alu: tidy up logic optimization...06:39
stekern*that*s how the rebased version should look like... git should warn if you try to push a branch you currently are doing a rebase on...06:40
stekernsb0: the bloat should be reduced from 1.6k to around 0.7k now, be sure to use p_FEATURE_STORE_BUFFER="NONE" to experience the full extent of it.06:45
stekern(that means we are still about 700 LUTs larger than lm32)06:46
stekerntrce claims you can run the papilio pro board at 90 MHz though06:47
stekernso we might have got slightly faster as well06:48
sb0how does the store buffer impact performance? does lm32 have one?06:50
stekernlm32 doesn't06:50
stekernand it improves performance under certain circumstances06:51
stekernit's a really simple implementation, stores are buffered up in a fifo, and the pipeline is not stalled until either: 1) the FIFO is full 2) there's a load in mem stage06:52
stekerni.e. no content based decision are made, and no content is read from the store buffer06:53
stekernso, it's useful for e.g. typical stack stores in function prologues, without having to resort to a write-back cache06:54
stekernit also have the advantage of making non-cached stores faster even if a write-back cache would have been implemented06:56
stekernand that's how cache-coherency for 'dma' operations under openrisc Linux currently works, cache is inhibited on those pages06:58
sb0hmm by board does not boot anymore07:01
sb0could be a ISE bug though. an unrelated code change made it boot ...07:04
stekernoh, did you expect it to be smaller *and* work? sigh, you are high maintenance ;)07:06
sb0I think it does work07:07
stekernok, great, I haven't tested running anything more elaborate than basic stuff on the changes, so there might be dragons07:07
sb0I've experienced similar breakages before, and they definitely look like ISE bugs07:08
sb0so, 884 LUTs to go ;)07:08
stekernI only got 732 as the difference on the ppro board07:11
stekernbut, yes, there's still room for improvement07:11
poke53282stekern: Finally I have managed to get linux recognize something which he assumes to be a sound device.07:34
poke53282This asoc abstraction is complicated.07:35
poke53282tomorrow I will try to get some signal out :)07:36
stekernpoke53282: cool!07:36
poke53282you need three devices in the dts file to get it work.07:37
stekernI'm currently writing some baremetal test code for the wb_streamer, so I'm hoping on getting some signal out soon as well ;)07:37
stekerncodec, config, dma?07:37
poke53282hardware, codec and a driver which connects both.07:37
stekernmy setup needs the opencores i2c driver, a ssm2603 driver and a wb_streamer dirver07:39
poke53282opencore i2c driver? Do you have a link?07:40
poke53282you mean ssm2602?07:41
poke53282I guess you need the "simple-audio-card" too07:42
stekernno, I mean ssm2603, but the ssm2602 driver probably covers that07:43
stekernI have baremetal drivers for both i2c and ssm260:
stekernso I figured the easiest forward to test wb_streamer is to just write a small POC with these07:44
poke53282Ok. Looks like, it would be easy to build a driver under Linux.07:49
stekernI know that my ssm2603 and i2c driver works, so then the only variable is the wb_streamer, without layers of Linux ASOC logic to potentially mess things up07:49
olofkstekern: You got a papilio pro?07:51
olofkAnd of course wb_streamer works. It's got a test bench :)07:53
stekernolofk: no, I just do misoc test builds against that to get some LUT usage numbers, it's a minimal soc that is quick to build07:54
stekernolofk: yes, but I might not have hooked it up correctly ;)07:54
olofkstekern: That's true. I sometimes forget that my sensitive code is handled by mortals07:55
stekern...and since there's no known to work driver for it, I was speaking about getting the sw side to work as well07:55
stekern+ I might want to upgrade sublime to use wb_streamer instead, so I'll need a baremetal driver then anyway07:58
poke53282you can send the sound also via network :)07:58
poke53282stream I mean07:58
poke53282also loop device.07:58
poke53282alsa loop device08:01
poke53282what I have seen, a backend hardware driver is not complicated to write.08:09
poke53282there are tons of example drivers. Some of them are really small08:09
stekernI remember that writing the ac97 driver was messy08:13
stekernbut maybe the asoc interfaces are less of a mess08:14
stekernhmm, the tinysid site doesn't seem to exist anymore :(08:16
poke53282You can use my online player
poke53282but there are tons of other players out there. Why tinysid?08:17
poke53282ahh, because of Linux?08:17
stekernthat, and it's tiny... and I have used it before08:18
stekernbut then on baremetal08:18
stekernI probably have the sources on my hd still somewhere08:19
poke53282Well, when I get sound running I will add a sid player if I find one08:19
stekern and
poke53282timidity, aplay, xmp08:19
olofkstekern: Added some tests for different buffer sizes in stream writer now. Looks like it works fine as long as buffer size is a multiple of burst length08:21
poke53282:) even with a small screen08:21
olofkRight now burst size is in words, and buffer size in bytes though. Not sure if that's how I want it08:22
olofkstekern: haha. Cool demos :)08:23
poke53282So, which sid-files where those?08:23
poke53282do you still have them?08:23
stekernpoke53282: the one with the old-school demo effects is done by yours truly08:23
stekernthe ones with the real sid chip is from various games (taken from HVSC)08:24
poke53282Ok, and the HVSC collection is huge .,, I mean really huge.08:24
stekernthat's the one and only sid I've made08:31
olofkHow did you make it? Are there any trackers available?08:32
stekernin goattracker iirc08:32
olofkTime to vote!08:43
stekernolofk: some wb_streamer feedback/questions09:54
stekernI'd like to see the 'enable' reg become a ctrl/status reg, where I could poll the completeness of a transaction (and the irq would be connected to that bit)09:55
stekernthe 'enable' would then just be a write-only bit in that reg09:55
stekernsecond, I haven't dug through the code yet, but what does 'buf_size' actually mean? is that in any way connected to the FIFO size?09:56
stekernor is it just "end address"?09:56
-!- expert is now known as PaulfraOSAA10:15
olofkstekern: (enable) Agreed. There's an internal 'latch_enable' that does exactly that. I should rewire and hook that up to the reg instead11:35
olofkbuf_size is the size of the memory area to read from (in bytes)11:35
olofkSo, yes start_addr+buf_size = end address-1. A very novel idea that I came up with. I should patent it :)11:36
olofkThe FIFO size just determines the maximum burst read length.11:40
olofkWell, start_addr+buf_size = end address+1 to be exact11:47
stekernright, that's what I figured, just wanted to make sure11:48
olofkThe component only handles full words. What would be the appropriate thing to do if someone sets start address or size to something unaligned?11:55
olofkJust ignore bits 1:0 and/or set an error flag?11:55
olofkNo l.rol in OpenRISC?12:08
stekernnope, no l.rofl neither12:08 :)12:09
stekernwith the new optimized barrel shifter in mor1kx, implementing l.rol would be no-cost12:10
stekernbut, since you can just do 32-rollbits in sw, it's really no point12:11
olofkAre both ror and rori class II instructions?12:11
olofkCouldn't find anything in the arch spec12:13
olofkBut then I extend the testcase to handle both12:14
stekernjust look at the instruction description for them and the footer12:14
olofkGreat. I see it now12:15
olofkSo, should the ror test be in mor1kx_cappucino.tests?12:29
olofkI guess not, since it will fail12:33
olofkOr do we want that turned on in mor1kx-generic perhaps12:37
olofkhmm.. should burst length be specified in bytes instead words as well?13:04
-!- expert is now known as Guest4242015:23
-!- Netsplit *.net <-> *.split quits: lauri, atgreen15:38
stekernis buf size in words?15:53
stekernor in bytes?15:53
stekernhmm... doesn't this mean 'end_address' and not 'buf_size':
stekernah, no, adr is not an adr, but an offset to start_adr16:17
stekernolofk: how d'ya like this?
stekernalso, this would be slightly cleaner than separately assigning active: assign active = (state == S_ACTIVE);18:03
stekernolofk: wb_streamer locks up after a couple of transitions19:35
stekernwithout probing deep, it looks like the fifo is signaling empty, but cnt != 019:35
stekern if wr_en & full or rd_en & empty can occur, then you already are in trouble19:44
stekernbut I bet that is accounted for elsewhere19:45
stekernat least the rd_en isn't connected straight to the fifo19:46
stekernI'll signaltap some more to see what's going on19:50
stekernI couldn't see anything obvious from the code19:51
stekernyou should update the fifo code from mor1kx btw ;)19:51
stekernfifo is signaling empty, but cnt = 0x1b20:23
stekernlooks like wr_en is asserted when full is asserted20:29
Guest42420Is there any place where I can learn more about fusesoc? I can't really seem to find any way to read up on where to go from the install20:36
Guest42420Specifically how I can configure the system to have other components (such as my own IP) and how to set up the memory map20:37
Guest42420I've rumaged around the fusesoc-systems, but can't find any place where a memory map is defined. I know that the blinkenlights program doesn't need a map, but in the setup olofk showed me there was one (and I wanted to try out C/C++)20:39
-!- Guest42420 is now known as PaulfraOSAA20:46
stekernthe memory-maps are defined in the wb_intercon.conf files20:50
stekernolofk: there are several problems with wb_stream_writer_ctrl21:11
PaulfraOSAAstekern: ok, found them. Thank you! Now I just need to figure out how to use the build system :)21:11
PaulfraOSAAGoodnight all21:11
stekern1) the fifo_cnt is delayed by two clock cycles from the write, but you only wait one cycle after the last write in a burst before you read it to determine if there's room for another burs21:13
stekern2) your end of wishbone burst will only work if the slave acks the last request directly21:14
stekernthis is how my (completely untested) modified version looks like now:
olofkstekern: (busy flag) Looks good21:44
olofkI might drop the fifo count and start reading on fifo empty instead. My original idea was to use the count as a watermark, but it's much simpler to just wait until the fifo is empty21:47
olofkAnd I should also make a memory model with variable ack delays. That would have caught the bug you found21:48
olofkstekern: I just improved the memory model to handle variable ack delays, and it works fine with your pasted wb_stream_writer_ctrl.v22:16
olofkBut it fails with mine22:16
--- Log closed Mon Sep 15 00:00:53 2014

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