IRC logs for #openrisc Monday, 2014-09-01

--- Log opened Mon Sep 01 00:00:32 2014
maxpalnquick question on the new adv_debug_sys top level - there is an output port called wb_cab_o, it isn't connected in either the atlys or de0_nano implementations. I can't see a reference to CAB in the wishbone spec so I'm not sure what to do with this signal. ANy cllues?08:54
maxpalnthat should, of course, be a request for clues not cllues!08:54
stekernmaxpaln: I'm not sure where that comes from, but there are references to wb_cab_o in or120008:59
stekernwith a comment that says 'consecutive address burst'08:59
stekernmaybe it was some custom extension they used before the bursting in wb b3 was defined(?)09:00
maxpalnmaybe, perhaps I'll just leave it hanging for now. I am not in a position to test this at the moment but maybe I'll revisit it if the debugger doesn't work.09:03
stekernI have never came across anything that actively use it09:07
maxpalnok, hopefully it won't become an issue!!09:12
stekernI highly doubt it will09:15
olofkI always assumed that the cab signal was just a tag that could be used to identify transactions11:28
olofkBut as stekern said, no one seems to have ever used it for anything. At least not in the last five years11:29
olofkOr perhaps NSA uses that for wiretapping11:29
olofkThis changes everything!11:30
stekernolofk: yes, I was also under the expression that it had something to do with tagging, but those signals are TGA, TGD and TGC11:32
olofkAh yes. That's right11:32
stekernand as maxpaln said, there's nothing in the spec about CAB11:32
olofkNote to self. Never implement a bus standard with a lot of optional extensions11:32
olofkWhat's the magic option for offsetting an output file with objcopy?11:34
olofkYes. That's it. Just got to that in the man page now11:38
stekernok, so, you ask *first* and then start reading the documentation? =P11:39
olofkNah, I had been reading it for a while without finding anything11:40
olofkhmm.. not quite there yet. IF I use a negative offset, the output file starts with the initial zeros moved to 0xffffff8011:42
olofkSo it's more like a rotate option11:42
stekernif the offset is negative and you have stuff at address 0, isn't it natural that that address become negative then?11:45
olofkWell, it's really only zeros from 0x0 to 0xff (standard or1k elf file)11:46
olofkWhat I could do is of course to remove .org 0x100 from the input asm, but what's the fun in that?11:46
olofkIt's for generating boot ROM btw11:46
stekernI see11:47
stekernbut why did an offset of -256 generate an inital start at -128?11:48
olofkI just tested both11:48
olofk0xffffff80 was probably for the -128 case11:48
olofkTrying to get the theory of this... does .text start at 0x0 or 0x100?11:49
stekern.vectors start at 0x011:51
stekernbut... I would cut those 256 bytes off from the binary instead11:54
olofkYeah, I've been doing that11:54
stekernbecause, even if you *might* not want them in your rom, you probably want them in your preloaded SRAM11:55
olofkAnd since objdump can't output 32-bit verilog mem files anyway, I'll just finish my python script that takes a binary as input11:55
olofkBut if I do objdump -x on my file, I don't see vectors anywhere11:56
olofkand .text, .data and .bss all start at 0x011:56
stekernwhat file do you have?12:01
olofkHow do you mean? It's a elf compiled from asm with or1k-elf-as12:02
stekernah, ok I assumed some or1k-elf-gcc compiled file when I mentioned .vectors12:03
-!- Netsplit *.net <-> *.split quits: imphil, arokux, jeremypbennett13:48
-!- Netsplit over, joins: arokux, jeremypbennett13:48
maxpalnThigs are looking good - I have a pretty up to date version of all peripherals, wb_intercon and MOR1KX in the design now - my last checkout was a month ago so there may be a few differences but essentially making good progress.15:14
maxpalnI was looking at the various memory controllers - the de0_nano board uses an interesting looking port_arbiter to allow multipler wishbone connections to the same memory - I have a similar setup in my design but I am just using the RAM example that shipped with the OR1200 design.15:15
maxpalnI wou;dn't normally bother to look at this any further (since the version I have works in HW) but the code looks messy and the de0_nano version looks pretty efficient. I am also getting glitches in simulation from the version I am using - which is ugly.15:16
olofkmaxpaln: Do you have an SDRAM on your board?15:16
maxpalnNope, a DDR3 memory -15:17
maxpalnI can see that the port_arbiter is only for the sdram15:17
maxpalnbut I more interested in the bit that allows multiple WB ports to access the same memory15:17
olofkYes. We want to separate that eventually, but right now the frontend and backend is glued together15:17
maxpalnah, ok15:18
maxpalnthe wb_port_arbiter code looks pretty neat - and nicely scalable (which the code I am using at the moment definitely isn't).15:18
maxpalnBut as I look into it I can see that it is pretty intitmately connected to the sdram controller.15:19
olofkYes. The source code is poetry coming from stekern's hands15:19
maxpalnWow - don't often get poetry references from a verilog file :-)15:19
olofkDefinitely bonus points if you can make a nice split15:19
maxpalnMaybe I'll take a look once the immediate pressures of getting this code working are removed.15:20
olofkBut if you're only looking for a way to share the memory between several masters, then wb_intercon will do that for you15:21
olofkThe stuff in wb_sdram_ctrl does some extra things like caching to make the external accesses more efficient15:22
maxpalnah, that's interesting - so in my case I have carried over the wrapper that is used with the ORPSOCV2 ram_wb component.15:25
olofkThat one is pretty crappy15:25
maxpalnso how would I setup the wb_intercon to mimic the same behaviour?15:25
olofkIf you want a memory that maps to internal memory resources, I suggest using wb_ram instead15:25
olofkSorry. Missed your last sentence15:26
maxpalnah, ok - I don't actually want the internal RAM. But the wrapper that MUXed the intstruction and data busses onto the same memory peripheral was useful - and indeed still is.15:26
olofkI see15:26
maxpalnbut if there is a way to get wb_intercon to do this bit then I would use it - the MUX wrapper is ugly code15:26
olofkYes. wb_intercon can do that15:26
olofkTiny example ->
olofkBasically, you create a slave port for the memory and let all the masters use it15:28
maxpalnso on your little example, on the 'mem' slave - how many wishbone ports would there be?15:30
maxpalnjust one, presumably.15:30
maxpalninterestingly I have something very similar in my wb_intercon - but have explicitly connected both instruction and data bus ports to my individual inputs ports on the memory MUX wrapper.15:31
olofkYou used the one from de0_nano for inspiration, right?15:32
maxpalnit sounds as though I can simplify all of this and just have a single wishbone port input to my DDR3 peripheral.15:32
maxpalnyep - the de0_nano looked like a good starting point - it's caused me a few headaches in the end :-)15:32
olofkThe reason why there are two in the de0_nano is that the wb_sdram_ctrl in this case contains it's own arbiter that is probably mor efficient15:33
olofkSo that one's a bit special15:33
maxpalnah, ok15:33
olofkOther than that, the de0_nano is probably your best starting point :)15:33
olofkBut beware if you do a fresh checkout. I changed things around a bit there last week15:33
maxpalnapart from the 8-bit to 32-bit resizing :-)15:33
olofkHaha. Right :)15:33
maxpalnbut the de0_nano was indeed a very good reference - I am basically hooked up and running now.15:34
maxpalnI doubt i'll need to revisit the de0_nano now - my project is working although in an independant way to fusesoc15:34
maxpalnbut this is a good staging point. Getting the code building in the fusesoc directory structure is probably the next one - then I can start to add support for our tools to the fusesoc system...15:35
olofkOne of the main ideas with the FuseSoC flow is that you should be able to just use the parts that you want15:35
maxpalnyeah, I am sure I'll be asking some questions when it comes to adding support for our tools.15:38
maxpalnjust looking at the way the wb_intercon has been hooked up based on my .conf file -15:38
maxpalnah, I see where I have gone wrong15:38
maxpalnI have created two slaves - one for the ddr3_ibus and one for the ddr3_dbus15:39
maxpalnI just need to create one slave15:39
olofkThat is not allowed in the free version of wb_intercon_gen. I demand that you send me money for the wb_intercon_gen EE edition15:39
maxpalnoh, yeah - of course, i'll upload my bank details now...15:40
maxpalncan you send me a suitably public website so I can maximise the potential for begin scammed...15:43
olofkI only deal in Fax and BBS15:44
maxpalnFax will work, I'll scan my credit card now...15:45
stekernfidonet ftw16:04
olofkGreat. It's just a regular +234 number16:22
olofkIt's for our nigerian office16:22
olofkbtw, maxpaln, you were planning to show up at orconf in Munich, right?16:23
maxpalnfunnily enough, I was just looking at the plans.17:30
maxpalnYes, I am planning on being there - it also sneaks into Q4 so getting budget approval will be much easier! :-)17:30
olofkHas anyone had success with wb_ram in hardware? I remember blueCmd_ said something about the burst stuff not working17:45
olofkAnd my led blinker doesn't work when I put it in the wb_ram, but it works fine in simulations17:46
stekernolofk: I bet it's in the logs17:50
stekerndo you have a de0 nano now btw? or what board are you playing with?17:50
olofkstekern: Yes. I have a de0_nano now. I'm actually doing paid OpenRISC work on it. Hope to tell more soon17:52
olofkI'm thinking of hooking up diila to see if I can find out what's going on with the burst stuff17:52
stekernthe 'new_cycle' logic is definetely buggy, but apart from that, I couldn't find anything by just reading the code17:57
olofkMe neither. And it works in simulations17:59
olofkBut when I debugged it for a spartan6, I noticed that there were some problems with some of the enable pins for the RAMs18:00
stekernadr = (wb_cti_i == 3'b010) & wb_ack ? next_adr : wb_adr_i;18:05
stekernis non-buggy, I think18:06
stekernwb_ack_o ;)18:06
olofkLooks like the memories are empty. Is there a handy memory inspector somewhere in quartus?18:15
olofkI'll try your solution and run through the sims btw18:21
stekernagenda for the tonights shift, add line-doubling to the vga_lcd core18:24
olofkcat * |wc -l tells me that it's 5010, so you expect to reach 10020 tonight? :)18:25
stekernnot quite =P18:26
olofkDisplay each vertical line twice?18:27
stekernand the horizontal18:28
stekernthe vertical are trivial18:29
olofkHorizontal does sound very much harder. Is it?18:29
stekernwell, you have to buffer a complete line (or re-read it from mem)18:30
olofkah ok18:30
stekernbah, this was kinda pointless... sw doesn't like resolutions < 640x400 anyway20:14
--- Log closed Tue Sep 02 00:00:34 2014

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