IRC logs for #openrisc Wednesday, 2014-05-14

--- Log opened Wed May 14 00:00:47 2014
pgavinI have a small pull request for orpsoc-cores if anyone is able to check it :)01:17
JakeUSCAnyone available to answer a quick question?02:47
pgavinJakeUSC: do you still have that question?02:55
JakeUSCYes I do.02:55
JakeUSCI am trying to get a soc running on my atlys board for a project, but I am getting into a snag.02:56
JakeUSCI built all the toolchains and synthed the fusesoc but I am not sure how to get a program into it02:56
pgavinhave you simulated the program with fusesoc?02:57
JakeUSCI see there is a rom.v that I should put a bootloader in but I cannot figure out how to convert the u-boot.bin into something I can add to the rom.02:57
pgavinyeah, I haven't done that02:57
pgavinbut one sec, I can look02:57
JakeUSCNo, I have not simulated. I am trying to get the u-boot standalone example into a format that I can load03:02
pgavinwell first try booting it in the simulator03:03
pgavinif you have an elf file you can use the --elf-load flag03:03
pgavinyou have a bin, so use the --bin-load03:03
JakeUSCok, Thanks. I am building the simulator right now. I'll have to read up on how to run it.03:04
pgavinsomething like: fusesoc sim --sim=modelsim atlsys --bin-load foo.bin03:05
pgavinactually I think only icarus is supported in simulation for that board03:09
JakeUSCYeah, it is giving me problems. Going to install that03:10
JakeUSCWARN:  File ../orpsoc-cores/systems/atlys/bench/orpsoc_tb.v doesn't exist03:19
JakeUSCWARN:  File ../orpsoc-cores/systems/atlys/bench/uart_decoder.v doesn't exist03:19
JakeUSCERROR: Failed to build simulation model03:19
JakeUSCERROR: Failed to compile VPI library elf-loader03:19
JakeUSCI think I may have to write a test bench03:19
pgavinnot sure about that one, sorry03:21
JakeUSCso assuming that I am able to get this sorted out, what is the best way to get a program on the soc?03:22
pgavinI think fusesoc will do it03:24
JakeUSCOk, thank. I appreciate the help. Going to work on this a little more tomorrow. Have a good one.03:27
stekernfor the record and our listeners on the irc weblogs, there are two issues that lacks proper support in the atlys fusesoc board port 1) simulation 2) boot rom03:47
stekernfor 1), the problem is, to properly simulate the complete soc, you need to use xilinx encrypted sim libs and AFAIK you can only do that with modelsim03:49
stekernmy own access to modelsim is very limited these days, so I can't really implement it myself...03:49
stekernfor 2), I think blueCmd started some support on this in03:50
stekernpgavin: thanks for the mor1kx-generic fix, I completely forgot to check that as I had promised :(03:55
stekernI pulled your request now03:55
stekernwould you mind checking if or1200-generic have the same issue?03:56
stekernnvm... your fix should of course cover that as well03:58
stekerngood that I was pushing on having most of the code in verilator_tb_utils ;)03:58
pgavinseems the changes I made to the gcc optimizer didn't help04:16
pgavineven though the code looked better04:16
pgavintrying to figure out why04:16
pgavinthe code was bigger for some reason04:16
pgavinI'm having to keep two copies of gcc to test it of course04:20
pgavinso I may have messed up somewhere04:20
pgavinso I'm rebuilding everything now04:20
pgavindoes mor1kx test the caches etc.04:21
pgavinok, it appears that it does04:25
pgavinbut the memory only has 1 cycle latency04:25
pgavinbut that shouldn't matter for this04:25
stekernpgavin: yes, we had some "random memory latency" in one of the simulation models for the block rams05:00
stekernnot sure if that made it into orpsoc-cores though05:01
stekernit was mostly to "mix things up" when running the tests05:02
stekernbut.. as you say, your point with the gcc optimizations shouldn't have anything to do with mem latencies, since it's the interlock you want to avoid, right?05:05
pgavinI changed the timing on the multiply05:06
pgavinI'm checking if that's what caused it05:06
pgavinit was originally set to 16 cycles05:06
pgavinI changed it to 2 cycles because the pipeline stalls anyways05:07
pgavinand can't execute past multiplies05:07
pgavinbut that might mean gcc is using multiplies instead of shifts etc.05:07
stekernok, is that a bad thing?05:08
stekern...reminds me that I should fix that, the pipeline shouldn't stall on mul...05:08
stekernat least not cappuccino05:09
pgavinif gcc thinks a multiply only takes 2 cycles, when it actually takes more than that, it might not substitute cheaper operations05:09
stekernwell, it doesn't take longer05:09
pgavinoh, how many cycles is multiply?05:09
stekern(not on mor1kx)05:10
pgavinsame as add or one more?05:10
stekernit's more, add is single-cycle05:11
stekernbut it might be 3 now when I start to think about05:11
stekernbut it really should only be 1 cycle, the result should be pipelined and written straight into the register file in wb stage, instead of stalling the pipeline05:11
stekern...that of course means that you'll need to insert bubbles on instructions after the mul that needs the result05:12
pgavinthat's how mine works05:12
pgavinexcept the multiply can be n cycles05:13
pgavinbecause I'm going to simulate asic05:13
stekernah, I see05:14
stekernhmm, interesting... I always considered changing mor1kx to have multi-cycle (well, more than three, that can go along with the pipeline into wb) as stalling the pipeline (as it does now)05:15
pgavinwell, mine still stalls05:15
pgavinI guess it wouldn't be too expensive to make it go past05:16
stekernaha, so you stall and the result is bypassed into wb stage?05:16
pgavinit can't be forwarded back to the ALU05:16
pgavinit just goes to the RF05:16
pgavinsame for load result and divide05:16
pgavinexcept load result can be forwarded to a store05:16
stekernright, that's what I want, but I also want the pipeline to not stall ;)05:17
pgavinyeah, that's extra state to track05:18
pgavinso I didn't do it :)05:18
pgavinprobably would be easy though05:18
stekernhmm, it's not that much overhead, I did it like that in my eco32 implementation05:18
pgavinI guess you only need to track the register number05:18
pgavinbut.. then when the result is ready you need to stall the pipe 1 cycle for the write05:19
pgavinunless the instruction isn't writing05:19
stekernhmm, not following you?05:19
pgavinRF only has 1 write port05:19
stekernwhen the result is ready, the mul is in wb stage05:20
stekernnothing else is trying to write to the rf then05:20
pgavinI guess mine is a bit different05:20
pgavinI have F D E M W05:21
pgavinresult for RF is muxed at end of M05:21
pgavinALU is at E, and caches are synchronous05:21
pgavinso address and store data are ready at end of E05:21
stekernthat's the multiplier in my eco32f05:22
stekernthen there's this to handle the hazards:
stekernand here05:23
stekern's the mux into the rf:
stekernthat's it ;)05:23
pgavinI guess I mean if the multiply lasts longer than 2-3 cycles05:24
pgavinthen you have to store the destination reg number05:24
pgavinand other instructions will get to writeback before it finishes05:24
pgavinI think you have 1 more pipe stage than me05:25
stekernah, yes, in the case it stalls...05:25
pgavinyeah, if other instructions can get to writeback before the mul completes, then you'll have to stall them05:25
stekernI do, but it's in the very beginning of the pipeline, before fetch, so it shouldn't make any difference05:25
pgavinI have that too05:26
pgavinbecause the icache is synchronous05:26
pgavinbut I don't really have a W stage05:26
pgavinwell, sorta05:26
pgavinI think I forward from there actually05:26
stekernwell, you can do without the extra stage before fetch even if the icache is synchronous05:27
pgavinit's not really a full stage05:28
stekernthe whole F stage is the icache read05:28
pgavinit doesn't have driving registers05:28
pgavinduring BF the PC is muxed05:28
pgavinthen F is the cache read and way select05:28
pgavinD is decode & RF read05:29
pgavinthen E is alu, M is dcache & way select05:29
pgavinI haven't checked timing so it might not be very good05:29
pgavinI suppose I should do that soon :)05:29
stekernok, I did the eco32f like that at first, but the timing was awful05:30
stekernbut it's a slightly different arch05:30
pgavinwe'll see05:30
pgavinthe PC mux is huge05:30
pgavinI bet that's where the critical path is05:30
stekernit doesn't have a separate set-flag insn, so the compare is in the branch instructions05:31
pgavinI have a few things in mind if that's the case05:31
stekern...PC mux is a problem in mor1kx at least ;)05:31
pgavinyeah, the branch resolution is practically straight off the register05:31
pgavinI have a way to trim off a couple of inputs to the PC mux but it means changing some things05:32
pgavinbasically to do with exceptions05:32
stekernyeah, you have to be careful with those, they can create some nasty paths05:46
stekernbut, still a question about the mul, so are you letting other instructions "past" the mul? At first, I thought your implementation stalled the rest of the pipeline when the mul arrives to wb, but it's not ready05:48
stekernbut your latter comments suggests otherwise05:48
pgavinit stalls in M if it's not ready05:50
pgavinthe operation is fed to the multiplier early in E05:50
pgavinoh, that reminds me of something05:51
pgavinexceptions will be difficult if you go past the multiply05:51
pgavinso you can only do it if OVE is off05:52
stekernok, but that's just a small detail, if it stalls in M or WB. The real question was if other instructions proceed "past" the mul05:52
pgavinI don't have that yet05:52
pgavincan your dcache handle a load immediately after a store without stalling?05:54
pgavinthat took me forever to get right05:54
stekerndoes all these overflow flags and exceptions actually make sense to have, does anyone really use them?05:55
pgavinwell, maybe05:55
pgavintiny dsp stuff could use it I suppose05:55
stekernyeah, I suppose...05:55
pgavinbut it's not hard to check if OVE is off05:55
stekernwell, at least they are optional, but they make some nice optimizations harder to do when you want to be able to opt them in05:56
pgavinlike I was thinking about the mac05:57
stekern(load right after store) hmm, good question, might be that we stall on that situation05:57
pgavinthe mac has exceptions now... so it has the same problem05:57
pgavinwe could change the spec to postpone exceptions until l.macrc though05:57
stekernor what did you mean, any load after store, or a load from the same address?05:58
pgavinany load immediately after a store05:58
pgavinbecause the store takes 2 cycles no matter what05:58
pgavinit might be worth putting that into gcc if not06:01
stekernyeah, no, we don't stall on that06:02
pgavinso you buffer the store somehow?06:02
stekernwe check for the write in ex stage, perform the write in mem, and then load is ready in the next cycle06:02
pgavinso when do you calculate the address06:03
stekernthe virtual address comes from ex06:03
stekernand the physical is ready in mem06:04
pgavinok, I misunderstood06:04
stekern...but, yes, we do have a storebuffer06:04
pgavinbut is that on the memory side?06:04
stekernthe storebuffer?06:05
pgavinso how does it catch loads to a store in the buffer?06:07
pgavinif it doesn't use a cam06:07
stekernso... sorry, yes, of course it will stall...06:08
pgavinah, ok06:08
stekernsince we don't track the addresses in the storebuffer06:08
pgavinok, so as long as there's something there it stalls loads06:08
pgavinso on mine, loads access tags + data at the same time06:09
stekernI was only looking at the cache logic, there's nothing there that'd stall a load after store, but the actual memory access will06:10
pgavinand stores do tags then write to store buffer, then data whenever it's free06:10
pgavinand a 1 entry store buffer seems to be enough, so I just use registers06:11
stekernah, cool06:11
stekernI tried to make the storebuffer in mor1kx as modular as possible, so it shouldn't be too hard to play with something similar there06:12
pgavinit will be easier because your cache is pipelined06:12
pgavinbut I needed to reuse the cache on another architecture06:12
stekern...since usually when you implement something, the real pain is the pipeline control logic06:12
pgavinit was hard to coordinate access to the cache structures with the store buffer there06:13
pgavinbecause you have in-flight stores that can be bypassed by later loads06:13
stekernso, is your cache after the store-buffer?06:14
pgavinand you have to keep track of whether the store was a hit... and a later load can pull the cache line out from under the store, so you have to watch for that06:14
stekernor am I just misunderstanding now?06:14
pgavinit checks the tags, then writes to the store buffer the cycle after06:15
pgavinand it *always* writes to the store buffer06:15
pgavinbut it can be forwarded straight to the cache if the store buffer is empty and it was a hit and there's not an incoming load06:16
pgavinso it's complicated :)06:16
stekernhmm, yeah, sounds like it ;)06:16
pgavinthe dcache is about half the number of lines of RTL as the cpu control logic...06:17
pgavinI may have overdone it06:17
stekernmmm... the one in mor1kx is overly large too...06:17
stekernthat's more spartan ;)06:18
pgavinyes that's small :)06:18
stekern...but has a lot less features too ;)06:18
pgavinI guess the fill control logic is in another file?06:19
pgavinok I need to go to bed before I mess up my sleep schedule again :)06:20
stekernolofk: using the cygwin version of svn worked better07:26
stekernbut, now I can confirm the issue that other user had07:27
stekernwith the paths07:27
olofkOh for fuck sake. I haven't been away that long, but I'm treated with the back log from hell07:59
raholofk: respond to my questions first! :-)08:09
rahme! me! me! :-)08:09
ysionneauI wonder if there is any point on having a license on a file containing only #defines :o08:18
ysionneaubasically I could just copy paste everything, change a bit the define names and relicense it?08:18
ysionneauthere is no intelligence at all in such a file, right?08:18
olofkrah: ahh.. right, you were talking about the ztex board, right?08:27
raholofk: I was08:28
raholofk: well, I was more interested in getting them to produce a board for OpenRISC08:28
rahthat is, an FPGA board with high-speed transceivers, intended to be used for an OpenRISC ASIC as well08:30
rahthey could be interested in putting something together08:30
olofkrah: Could be worth talking to them about it. Their current boards aren't really suited for what I'm interested in08:31
olofkams: Morning08:31
raholofk: if you want to put together that list of requirements, I'd be happy to contact them08:32
olofkrah: But it's interesting to see the price tag. I guess that the board I'm looking for will be quite expensive. Not sure how expensive though. $1000? $2000?08:32
olofkrah: Sure. I'll do a brain dump when I have some time08:32
olofkjuliusb: The plusargs scraping is pretty cool, right? I'm damn proud of that part :)08:34
_franck__olofk: rah I would be very interested to work on an OpenRISC board (that's my job, I can do schematics and layout)08:35
olofkAnd way to go with the or1k-headers proposal. I think we have discussed it before, but it never took off08:35
olofk_franck__: That's awesome! We should think a bit about what we would want on a board08:36
_franck__sure. I don't use free EDA tools, would it be a problem if I had to design something ?08:37
olofkI wouldn't care if you use dead puppies do design the board as long as it gets done :)08:38
olofkblueCmd: Good news about gentoo, and of course there's room for one more on our short family bus08:40
olofkCan someone help me with git-allocate-origin btw? I'm not sure why it's not returning COMMANDEER_REMOTE_SUBMODULE08:40
stekernysionneau: I completely agree with you on that...08:41
olofkstekern, pgavin: I've been planning to do a smarter memory slave based on wb_bfm that can be used to simulate various delays and error conditions08:41
stekernolofk: I see you then treat us the ame way, I just went for lunch and you managed to fill a whole page of backlog...08:42
olofkpgavin, stekern: There's a wb_bfm_memory.v in wb_bfm that could be extended, preferably with run-time parametrization08:44
stekern_franck__: it would be fun if it could be done with kicad, but yeah, dead puppies are ok too ;)08:46
_franck__stekern: well, it would be way more work for me. I'm working with orcad and Cadence Allegro for years08:51
_franck__however, I did an orcad netlist to kicad converter some times ago....but still08:52
rah_franck__: cool :-)09:02
rahis anybody here buying a Novena "laptop"?09:04
stekernnot me09:20
stekernhonestly, I think they made a mistake moving away from the conventional "laptop" layout09:20
stekernnow it's just a dev-board in a box09:21
ysionneauahah olofk nice website :)09:21
stekernI got: git-skirt-upstream09:24
rahstekern: I completely agree09:25
rahI was bitterly disappointed when they came out with their final design09:26
rahI was looking forward to a free hardware (clam-shell) laptop09:26
stekernyeah, I think I actually could have considered buying such09:27
stekernI don't know if I actually *would* have, but the current design I'm not even considering09:27
rahI definitely would have :-)09:27
rahbut I'm not with the current design09:27
stekernI want a clam-shell laptop with the 10" ipad screen...09:28
stekernwell, maybe it's not a "laptop" then... but I want the conventional design with keyboard09:29
rahI spoke to bunnie in their IRC channel, he said the reason they didn't do a clam-shell was because a clam-shell would have required four molds for the injection molding, which cost $100,000s each; it would have made it four times as expensive so they did something that would be reasonably achieved with a crowd-funding campaign09:29
stekernok, I guess that's a fair reason then.09:30
stekernstill a pity09:30
rahwell, I asked him why he didn't make a clam-shell lid using aluminium instead of injection-molded ABS since it's obviously not necessary for the stiffness as the current design has an aluminium lid09:30
_franck__with 3D printing you could avoid injection molding09:30
rahhe didn't respond to that :-/09:31
rah_franck__: good point09:33
stekernysionneau: to get back to your comment on spr-defs.h, even if I agree with what you said, that's not how copyright law works. It doesn't care about logic, even comments are covered by copyright.09:58
olofkysionneau: Yep. Guess who's twitter account I have to thank for that link :)10:34
ysionneaustekern: is it OK with copyright law to copy the file, remove comments and rename macros ?10:44
ysionneaubecause I don't know how else you can do10:45
rahysionneau: no, that would not be OK10:45
ysionneauif that does not work, then it's the same as saying you are copyrighting the values of the defines10:45
ysionneauwhich is really strange10:45
rahysionneau: the critical word there is the "copy" in "copy the file" :-)10:45
ysionneauok, let say I don't copy the file, but I write with my hands one by one the same defines but with other names :)10:46
stekernlaw is strange ;)10:46
rahwhat is copyrighted is the output of someone's actions10:46
rahso the contents of this particular file is different from an identical file produced by someone else typing the file from scratch10:46
rahunless they're typing the content of the other file, in which case it's copying :-)10:47
rahI mean, if they look at the other file and just type it in again, that's copying10:47
ysionneauthat's just total nonsense :(10:47
ysionneauI prefer not understanding10:47
rahif they know the values and write them out into a new file, which ends up being identical to the original, then in copyright law that's OK10:47
ysionneausorry for bringing this topic :)10:48
ysionneaurah: ah, interesting10:48
amsrah: uhm, removing comments and renaming macros if perfectly fine under copyright law10:48
rahalthough, proving to a court that you actually created an identical file would be an interesting challenge :-)10:48
rahams: it is10:48
amsuhm, no, it isn't.10:49
rahams: but you can't then change the license of the result, on account of not being the copyright holder10:49
amsrah: who said anything about changing the license?10:49
amsunder copyright LAW it is perfectly fine.10:49
stekernams: that's what the discussion is about10:49
amsyou can have a particular LICENSE that prohibits such things; a non-free software license for example.10:49
stekernbut since the license is built upon copyright law, it is related10:49
amsand since a copyright license falls under copyright law, it means that it is allowed to do so under copyright law.10:50
rahams: there would appear to be a misunderstanding about what the word "that" referred to when I said "that's OK"10:51
amsthus, copyright law does allow you to modify comments, remove them if you so wish, and rename macros.10:51
ams12:44 <ysionneau> stekern: is it OK with copyright law to copy the file, remove comments and rename macros ?10:51
ams12:45 <rah> ysionneau: no, that would not be OK10:52
amsit is perfectly ok under copyright law to do so.10:52
rahams: you're missing the context I think10:52
stekernyes, but the underlying original question doesn't show in that, which was *and change the license*10:52
rahams: there is, in effect, tacit knowledge that isn't evident in the question or the answer10:53
ysionneauyes sorry, I meant then change the license10:57
amsrah: the context is the question, and your answer is wrong.10:59
stekernfine, if the only point of discussion is being right, you're right11:00
olofkIf this is a problem in practice, could juliusb relicense mor1kx-sprs.v to some ultra-liberal open source license and we can scrape the SPR info from there?11:01
amsi would call the file trivial in either case ... it is just definitions11:02
stekernolofk: it's already pretty much 'ultra-liberal' I think11:02
amsi.e. if you can mechanically generate that file anyway, then it cannot be copyrightable since it is just a list of "facts" or something...11:03
stekernams: yes, I agree, but I think *just* taking that exact file and slam another license on it might raise some eye-brows, even if the complaints would just be theoretical11:03
stekernpersonally, I'd be perfectly fine with it ;)11:03
olofkstekern: Right. I haven't looked at the OHDL really. Sorry juliusb11:03
amsstekern: i'd just contact all people listed and get an ok; it isn't hard ... this discussion takes longer.11:04
stekernit's hard... because all people listed don't tend to respond to openrisc related things11:04
amsi only see two copyright holders listed.11:04
olofkams: Which file? We got like twenty slightly different spr-defs in our tools11:05
amsolofk: only did a quick look, and only found two copyright holders listed ... could be missing something.11:06
rahI should point out that the GPL is limited when it comes to headers11:07
olofkotoh you could be completely right. Just wondering whih file you looked at :)11:07
amsrah: what do you mean?11:07
rahno sorry it's the LGPL that's limited11:10
stekernams: two is enough, if one of them is the non-responding part ;) besides, copyright isn't limited to names listed (even though it probably will be *damn* hard to enforce it without your name listed)11:10
olofkblueCmd, stekern: Did you check binutils in opencores bugzilla during the upstreaming?11:11
rah"If such an object file uses only numerical parameters, data structure layouts and accessors, and small macros and small inline functions (ten lines or less in length), then the use of the object file is unrestricted"11:11
rah(LGPL v2 section 5)11:11
amsrah: nothing to do with headers.11:11
rahams: I disagree11:11
stekernolofk: don't think we did, is there something particular?11:11
amsrah: and the lgpl agrees with me.11:11
rahams: I don't think it does11:11
olofkBug 31 for example.11:11
amsrah: it says right so, "then the use of the OBJECT file is unrestricted"11:11
amsrah: and there is no word of header in the whole license afair11:12
rahams: "When a "work that uses the Library" uses material from a header file that is part of the Library, the object code for the work may be a derivative work of the Library even though the source code is not. Whether this is true is especially significant if the work can be linked without the Library, or if the work is itself a library. The threshold for this to be true is not precisely defined by law. If such an object file uses only numerical parameters, d11:12
ams(there cannot be, since numerical constants could be in a .c file ..)11:12
olofkIt's probably not fixed in or32, but we could point people to or1k if it's fixed there11:12
amsthe whole concept of header files is alien to the lgpl.11:12
olofkAnd blueCmd told me that Dwarf2 is done, which should close #2511:13
amsolofk: cool11:13
stekernolofk: ah, right11:13
rahams: I think you're wrong on this one I'm afraid11:13
amsrah: uhm, no, the lgpl cannot talk about headers, simply beacuse headers are an artifical invention.11:14
rahams: the lgpl can and does talk about headers11:14
olofkGot a few more here that should be checked
rahams: if you read the quote I pasted above, you will see the word "header"11:14
amsrah: the lgpl uses header as something vastly different than what you mean, i mean headers in the C sense.11:15
amsand in that setting, there is no difference between including a .c file or a .h file.11:16
amsback to work.11:16
rahams: in what sense does the lgpl use "header" that is vastly different from what I mean?11:16
rahams: I think the lgpl uses "header" in exactly the same way that both you and I use it11:17
olofkstekern, blueCmd : Would be awesome if you could take a quick look at bugs 20, 21, 25, 31, 61, 62 and 6311:24
stekernolofk: I'll try to remember to take a closer look11:24
olofk_franck_, ams : You're the gdb gurus, right? Do you have anything to say about ?11:25
olofkLoneTech: We should probably make some noise on the list about . That's a pretty bad bug, right?11:25
stekern25 is definitely fixed in or1k, I remember that I looked at that and confirmed that the 'workaround (disabled)' could be removed11:26
* olofk calmly steps away from OpenCores bugzilla11:26
olofkstekern: Great. Will you do the honours?11:26
amsolofk: not the same libraries used for binutils/gdb?11:27
olofkams: Haven't got a fucking clue :)11:27
amsisuspect that is the case, gdb was compiled against bfd/whatever/else that does not coincide with the one for gas/objdump11:27
amshence why gas/objdump wrok, and hdb disassemble does not.11:28
stekernolofk: so what should I write there? that it's fixed in or1k, and leave it open?12:02
stekernsince the bug is directed towards a certain binutils version and has or32 written over it12:03
LoneTecholofk: perhaps. but I don't think I have much to add to the comment12:13
LoneTechthe MAC function itself is a rather odd addon, reminescent of how the FPU attaches in x8612:13
olofkstekern: Or maybe set it to resolved wontfix. I don't think anything more will be done with the or32 port12:49
stekernok, yeah, that's probably the best option12:49
stekernumm, I don't know how to log in to the bugzilla... =/12:50
olofkshould be your opencores account with email as username12:51
stekernI don't think I'm allowed to change the status of it though12:52
olofkSounds fair. I wouldn't trust you with such sensitive matters13:21
olofkstekern: Write a comment and ping jeremypbennett. Looks like he's the owner on all of the bugs13:25
stekernbug-owner, that's a fany title, aint it?13:39
jeremypbennettolofk: stekern: I thought you were also Bugzilla admins. I can make you admins14:24
stekernI don't get slashdots commenting system, there seems like there's always missing comments, even when you click 'all'15:22
stekernah, you have to move the lever...15:23
fotis2hey there... anybody here in the Benelux vicinity and attending a meeting?15:34
fotis2or, just feeling like demoing experience with OpenRISC builds?15:35
* rah <- Node16:04
rahstekern: I'm not sure fiddling with the lever is such a good idea :-)16:04
pgavinarah: yeah, it's really frustrating to read near-sighted comments such as this one: Absolutely nothing over any of the well supported and understood open source MIPS implementations. This is just another cause-we-can hobby project on the front page of Slashdot.17:39
juliusbolofk: wow, that was such a good update you made it to slashdot! well done mate18:54
mor1kx[mor1kx] wallento opened pull request #12: bus_if_wb32: Don't access bus on reset (master...master)
mor1kx[mor1kx] wallento closed pull request #12: bus_if_wb32: Don't access bus on reset (master...master)
ysionneaucrazyly full of non-sensical comments20:05
ysionneauon a more serious topic, I'm not sure you really need atomic ops (as some suggest in the comments in slashdot)20:06
ysionneauI guess you can always use the suboptimal RAS CAS, right ?20:06
stekernCAS as in compare-and-swap? RAS as in ...?20:11
LoneTechthose sound like address strobe lines for SDRAM to me20:12
LoneTechthe epiphany uses a test-and-set instruction for atomics20:13
LoneTechthere are a few different solutions, load-linked/store-conditional is one20:14
ysionneauRAS as in Restartable Atomic Sequence20:14
ysionneauyou have a symbol "ras_begin" noting the start of the RAS code20:15
ysionneauthen a "ras_end"20:15
ysionneauupon preemption, when you resume the code, you check if PC is inside [ras_begin:ras_end]20:15
stekernquick read-up on that suggest it's only for uniprocessor systems20:16
ysionneauif it is, then instead of restarting where you were, you restart at "ras_begin"20:16
ysionneauah yes, I guess indeed20:16
ysionneauit's just to allow preemption without having atomic ops20:16
ysionneauwhen you start going multi core ... maybe it's more complex to use that20:17
ysionneauor impossible :)20:17
ysionneauthat's what I used for my NetBSD port20:17
stekernmulti-core, that's what we're aiming for atm ;)20:17
ysionneaubut I only have uni CPU :p20:17
ysionneauyes sure :)20:17
LoneTechit's the same concept. ll/sc (called l.lwa/l.swa in openrisc) are the detection method for that preemption done by other hardware20:18
ysionneauwas just reacting to all those comments "how did you do before without atomic ops ? / you don't need them / yes you need them if you want preemption/ etc"20:18
stekernright, at least for uniprocessor, you definitely can get by without them.20:20
stekernblueCmd: your prophecy about a plethora of different types of implementations have came true in the form of spinlocks20:28
stekernsome archs use ticket spinlocks, some don't, some use negative values, some use 0 and 1 to indicate if the lock is taken or not.20:30
olofkWow... Slashdot. Never imagined that. Even though Slashdot is getting crappier for every year, the geek in me feels very proud22:04
olofkOh.. and it did wonders for my statistics  :)22:04
olofkI'm so going to get laid when I tell the chicks about this!22:06
skip__congratuations olofk :)22:11
_franck_stekern: blueCmd : is that a reason why we don't have __HAVE_ARCH_MEMCPY (with an asm version of memcpy doing word transfert and handling aligment) in the kernel ?22:13
olofk_franck_: I know that we have discussed that before, but I can't remember what was said22:14
_franck_I would have said that the Kernel doesn't use the GCC memcpy but now I'm not sure. It is linked with libgcc right ?22:19
--- Log closed Thu May 15 00:00:49 2014

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