IRC logs for #openrisc Friday, 2014-04-18

--- Log opened Fri Apr 18 00:00:10 2014
blueCmdstekern: *puh*
blueCmdI think that fixes the crash01:18
stekernblueCmd: nice!06:49
stekernI'll take a look at the commit later, when I'm not on siljas crappy wifi on my phone ;)06:50
stekernon my way to the motherland for easter06:50
stekernI assume it's TLS related, and that I only understand a fraction of06:51
stekernolofk: no fpu, the task os all open for you to take on!06:52
stekernbut, as you probably know, the or1200 one isn't 'or1200', it's an external one with a bit of 'hooks' into or1200. should be possible to do that with mor1kx too06:57
stekernnot sure of the license on that fpu cpre though06:58
blueCmdstekern: thanks08:44
blueCmdstekern: the human readable version: I think it was a race depending on which relocation was read first and that TLS and non-TLS locations would change the sreloc pointer in the section back and forth08:45
blueCmdI was very tierd when writing it so it might be 100% wrong, but it causes the linking to succeed and my basic tests works.08:47
blueCmdmpfr doesn't seem to enjoy life much more though08:47
stekernhmm, yeah... can't say if it's right or wrong without context switching into bfd and spend some hours learning about TLS ;)09:53
stonersantapoke53281: Have you had the time to look into node?14:44
poke53281Yes, but the emulation hangs after some seconds17:04
stonersantahmm, i whonder why17:08
poke53281I don't know, but will find out17:17
stonersantacool ^^17:18
olofkI can confirm that my wb_ram component does not work in hardware18:27
olofkAt least not on my spartan6 device.18:27
Limbolofk: Told you :P18:27
olofkBut I haven't got a fucking clue what's wrong. It works fine in simulations18:27
Limbolofk: It looks to me like it is creating the ram blocks on the board as well18:28
olofkLimb: Yeah, and it was good that you told me. Otherwise I wouldn't have suspected it and probably gone insane18:28 down for anyone else?18:28
Limbbeen having problems accessing it latley18:28
olofkLimb: I've seen that too. And the RTL schematic looks fine as well. Can't figure out what's wrong18:28
olofkJust tested. Can't reach it18:29
Limbsigh.. why does this code work one day and not the next18:31
Limbcan't get led blink to work with cell ram.. although it worked yesterday18:31
Limbannnd now it works -_-18:32
Limbcurious why reg npc starts at 0x200 on boot18:33
Limbshould be 0x10018:34
LimbHow do i view the output of a elf so I can verify where the contents are?18:35
olofkLimb: You can use or1k-elf-objdump -S <file.elf> to get a disassembly18:36
olofkIn general, use objdump or nm with the right arguments18:37
Limbolofk: thanks :)18:40
Limbshould reg npc increase as code executes? or no?18:43
LimbWell.. Doesn't lool like the de0 vmlinux image will work out of the box on the nexys :P18:55
olofkLimb: It should work...more or less19:07
Limbolofk: I get nothing on UART when i connect19:08
olofkAre you running on the same clock frequency? Might have to adjust the device tree file otherwise19:08
olofkSame as de0 I mean19:08
Limbde0 runs at 50 or 100?19:08
olofkI would guess 5019:09
LimbI'm using the precompiled image from the orconf wiki page19:09
LimbAnd my clock is set to 5019:09
olofkSame base address for the UART?19:10
olofkShould be 0x9000000019:10
Limbolofk: yep19:12
Limbstarted at reg 0x10019:12
Limbthat would be the correct one for the image no? Tried to verify with the elf dump and it looked so19:12
olofk0x100 is the default start address for OpenRISC19:13
poke53281stonersanta: Got it, but there are problems with responsive infinite loops in node.js. And threads (web workers) are only available via an addon.19:45
poke53281the "setTimeout(function() {.... }, 0);" function in node.js has another behavior than in browsers.19:47
poke53281instead of triggering the function right at the same function as setTimeout is called, it is waiting at least 1/64th of a second.19:48
LimbHow exactly do i get the system to boot the linux image/21:54
Limbjust upload and resume?21:54
Limbor do I have to do anything special?21:54
blueCmdupload and reset usually21:54
LimbblueCmd:  I don't have to type anything in uart?22:02
LimbI don't understand how this code works once, but I switch uart tx and rx pins and all of the sudden i get crc errors with openocd22:23
blueCmdtx and rx is always a problem22:48
blueCmdinsanely hard to know which endpoint they refer to22:49
Limbdoes anyone have example of simple uart i can compile and check?22:49
blueCmdLimb: no, it will boot just fine - you have to make sure the default arguments are fine though (the default is something like console on ttyS0 with 115200 baud 8n1)22:50
blueCmdLimb: you could copy the UART code from the kernel if you want to22:50
blueCmdthe early UART code from the kernel should be pretty stand alone22:50
blueCmd(the code that prints stuff like 'Uncompressing kernel ...' )22:51
LimbblueCmd: 115200 8n1 is the default?22:51
LimbHow do i go about setting up my own kernel exactly?22:52
LimbI assume I have to define my board somehow22:52
blueCmdLimb: clone the git repository for or1k-linux (jonas' repository), create a dts file in ./arch/openrisc/boot/dts/ with the board configuration and set CONFIG_OPENRISC_BUILTIN_DTB22:54
LimbblueCmd: reg = <0x00000000 0x8000000>;23:23
Limbthat look correct for 16 MB ram?23:23
Limbi dont understand why any change throws everything to disarray23:44
--- Log closed Sat Apr 19 00:00:11 2014

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