IRC logs for #openrisc Thursday, 2014-03-13

--- Log opened Thu Mar 13 00:00:18 2014
blueCmdman, I this is weird. I got this to work sort of once. I have the SOF covered, that works - I can cold boot it and start openocd (although I need to start OpenOCD twice, the first time it is never able to connect after a cold boot)00:38
blueCmdmdw 0x100 does _not_ read my vmlinux image. i got it to do that without using load_image once, but I'm not able to reproduce that00:38
blueCmdcurrently mdw 0x0 and mdw 0x0 reads 0ff00ff0 which seems like some sort of init value for the ram.00:39
blueCmdI looked at and used relative address 0 (since I the ihex I have seems to map perfectly fine starting at 0x0 and the CPU should jump to 0x100 when the boot rom is executed)00:41
blueCmdstekern: olofk: any relevant ideas regarding how to debug this would be helpful00:42
blueCmdnow, sleep.00:42
stekernblueCmd: what do you mean by "i got it to do that without using load_image once, but I'm not able to reproduce that"?03:50
stekernare you trying to cold boot the board with orpsoc and a vmlinux in the flash?03:53
stekernit wasn't really clear from your decription what you are trying to do when it doesn't work ;)03:54
stekernif so, the bootrom need to read the vmlinux image from the flash in order for that to work03:57
stekerninto the RAM that is03:57
stekernI don't think the infrastructure to build a rom like that is available in orpsoc-cores, but you can easily steal the .S for it from orpsocv203:58
blueCmdstekern: i see. so my thought was that the FPGA, while reading the SOF would simply do a JTAG write of the rest of the contents08:35
blueCmdstekern: "are you trying to cold boot the board with orpsoc and a vmlinux in the flash?" yes08:36
blueCmdsorry for being uncomprehensive - i tend to be that when I have hours of thoughts to dump08:36
blueCmdstekern: so basically I need a boot rom that reads the flash and writes the SDRAM?08:42
blueCmdand the reason I got it to work once was probably because of luck and the RAM just kept it's state. that explains why it booted and crashed halfway though the boot08:42
olofkA boot rom generator would be a nice addition to orpsoc-cores08:44
olofkIt's been on my TODO list for quite a while08:45
blueCmdolofk: it won't be much longer08:50
blueCmdstekern: ah, looking at the orpsocv2 code a lot of things feel into place in my head, thanks08:58
stekernblueCmd: yup, seems you've got the picture clear, and I was thinking the same, your one-time working scenario was probably because of RAM still containing old data09:01
blueCmdstekern: fun thing, I actually wrote a boot rom a while back. ( - simpler but the same concept :)09:06
blueCmdI guess I put too much faith in the Flash loader in the fpga09:08
olofkJust done some spring cleaning. Only four exit(1) left in the fusesoc module. Feels good09:31
olofkIt would be cool if someone would do a GUI around fusesoc. Don't know what it should do, but it's fun to click at things09:32
olofk_franck_: Does the resize function in wb_intercon_gen work? It looks like the slave port is still 32 bits10:00
_franck_web_it doesn't generate port in the rigth size. However those ports are 8 bits,  bits [32..8] are not connected10:04
olofkah ok10:04
_franck_web_should be fix (but I think it wasn't trivial so I left it for someone else :))10:05
olofkNo, the code in wb_intercon_gen is surprisingly messy. I'll just change the port size manually for now10:05
_franck_web_what do you mean by "No" ? You meant don't fix it but rewrite it completely ?10:09
olofkForget that "No". It was just a typo10:10
olofkBut next time we want to add a feature to wb_intercon_gen, we might have to rewrite it. But I guess that's up to whoever changes it next time10:11
_franck_web_That's a mess, I agree10:13
_franck_web_May be I'll do it since I would like to practice my Python skills10:13
stekernvhdls restriction that you can't read an output port is as stupid as verilog making a distinction between reg and wire.10:52
olofkYes. Those languages are equally fucked up, but in different ways11:38
stekernmmm, you could make a perfect or a really screwed up solution by combining them12:06
stekernperfect is perhaps stretching it, but...12:06
olofkstekern: BTW, the VHDL limitation is removed in vhdl200816:21
olofkie. You can read outputs16:21
stekernthat's nice, a lot of the really stupid things in vhdl is solved in that16:30
stekernmaybe I should just secretly switch all projects at work to use that16:35
blueCmd - openrisc debian build server22:59
poke53281What FPGAs do you use?23:13
poke53281You should eat the banana.  Does not look good anymore;)23:13
--- Log closed Fri Mar 14 00:00:19 2014

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