| --- Log opened Tue Mar 11 00:00:15 2014 | ||
| julzmb | blueCmd: Im taking a verification course and the | 02:15 |
|---|---|---|
| julzmb | big project is to develop a testbench for this core | 02:15 |
| stekern | quartus is not my friend anymore, it manages to come up with that 'mem' is "asynchronously read in this and thus fails to infer it as RAM: https://github.com/skristiansson/eco32f/blob/master/rtl/verilog/eco32f_simple_dpram_sclk.v | 06:17 |
| olofk | julzmb: a testbench for xge_mac? | 07:29 |
| blueCmd | julzmb: xge_mac? | 08:54 |
| blueCmd | that's awesome | 08:55 |
| blueCmd | stekern: weird | 08:57 |
| LoneTech | stekern: Altera seem to have had some trouble with inferring read enables, some old but helpful results at http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ | 09:07 |
| stekern | yeah, the funny part is that it depends on what I hook up to the read port | 09:42 |
| stekern | and the place where it have problems with it, the read-enable is tied to 1 | 09:42 |
| LoneTech | probably a couple of layers of optimization interfering with each other and generating ever so helpful messages | 09:44 |
| stekern | yeah, my suspicion as well | 09:44 |
| LoneTech | perhaps if it was told that it may not move that register? | 09:46 |
| LoneTech | something like reg [] rdata /* synthesis preserve */; might make the second optimization stop merging things. then again, it might also prevent it being absorbed by the blockram. I haven't tried it | 09:48 |
| blueCmd | olofk: atlys (xilinx) with fusesoc, yay or nay currently? | 19:41 |
| blueCmd | basic recog says nay | 19:41 |
| _franck_ | blueCmd: fusesoc doesn't support Xilinx tools for now | 20:15 |
| blueCmd | _franck_: ack | 20:24 |
| julzmb | olofk, blueCmd: Yeah It already has a good OOP SV testbench so this is mostly an academic exercise | 20:48 |
| olofk | julzmb: No testbench is good enough ;) | 21:02 |
| -!- Netsplit *.net <-> *.split quits: olofk, chad | 21:33 | |
| _franck_ | olofk: what do you think of having *all* sections in sections.py ? | 21:33 |
| _franck_ | I did some test with verilog section: http://pastie.org/private/pimcxrrdpid8lenbf3ovja | 21:33 |
| _franck_ | so we could remove verilog.py and vpi.py | 21:34 |
| -!- dalias_ is now known as dalias | 21:36 | |
| -!- Netsplit over, joins: olofk | 21:38 | |
| -!- Netsplit *.net <-> *.split quits: pgavin, enghong, ams, enghong_, poke53281, knz_, erdic | 21:39 | |
| -!- Netsplit over, joins: chad | 21:40 | |
| -!- Netsplit over, joins: knz_, enghong, erdic, pgavin, poke53281, ams | 21:41 | |
| --- Log closed Wed Mar 12 00:00:17 2014 | ||
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