| --- Log opened Sun Feb 02 00:00:19 2014 | ||
| --- Day changed Sun Feb 02 2014 | ||
| stekern | morning all | 02:40 |
|---|---|---|
| Powermaniac | Weird question: Could someone implement an open FPGA architecture on an FPGA? Or atleast could someone design an FPGA in say VHDL or Verilog and use the current tools to make a netlist of the FPGA architecture? As I've been doing some reading and it seems the industry would really like an open FPGA architecture that has an open toolchain, right? | 07:04 |
| Powermaniac | Again first someone (e.g. myself would need to know how to write VHDL or Verilog) then manufacturing an open FPGA architecture I imagine is not going to be cheap let alone easy, probably the same problem as manufacturing the OpenRISC architecture | 07:12 |
| Powermaniac | Although it does give me interesting things to explore at university whenever I get in that is...=\ | 07:12 |
| -!- Powermaniac_ is now known as Powermaniac | 10:38 | |
| -!- Netsplit *.net <-> *.split quits: julzmb, rah | 10:40 | |
| Powermaniac | Do any of you guys know Bunnie? From bunniestudios? | 10:46 |
| Powermaniac | Well don't need to worry about you guys knowing Bunnie think I worked out his email... | 11:46 |
| -!- rah_ is now known as rah | 18:24 | |
| -!- Netsplit *.net <-> *.split quits: vxe | 19:06 | |
| -!- Netsplit over, joins: vxe | 19:15 | |
| -!- julzmb_ is now known as julzmb | 19:26 | |
| olofk | Who the hell thought that using git was a good idea? | 20:28 |
| --- Log closed Mon Feb 03 00:00:22 2014 | ||
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