| --- Log opened Tue Sep 10 00:00:49 2013 | ||
| stekern | olofk: I came up with simple workaround for adding the .qip file to the project until we support that properly | 07:11 |
|---|---|---|
| stekern | just add a 'set_global_assignment -name QIP_FILE ../src/qsys/synthesis/sockit.qip' in a .tcl that is included in tcl_files | 07:12 |
| stekern | in the end... I might just manually instantiate the hps in orpsoc_top.v | 08:29 |
| stekern | let's see if I need anything else from qsys first though | 08:30 |
| stekern | right now, it's just a AXI<->avalon bridge | 08:31 |
| stekern | would make more sense for us to have a AXI<->wb bridge ;) | 08:31 |
| stekern | ah, there's actually a lot more things going on inside the hps module that is generated as well | 08:34 |
| stekern | so, maybe it's not feasible to do that | 08:34 |
| _franck_ | I have some verilator questions | 09:08 |
| _franck_ | I have an existing testbench: https://github.com/fjullien/jtag_vpi/blob/master/bench/jtag_vpi_tb.v | 09:08 |
| _franck_ | shoul I just remove the clock generation in my exsiting testbench and create a cpp testbench with a clock generation | 09:09 |
| _franck_ | like top->clk = !top->clk; | 09:09 |
| _franck_ | top->eval(); | 09:10 |
| _franck_ | stekern: do you have any verilator testbench of any of your simulated soc to show me ? | 09:11 |
| stekern | hmm.. I have only used the mor1kx-devenv (which is essentially orpsocv2) | 09:16 |
| stekern | but it's here that stuff is done: https://github.com/juliusbaxter/mor1kx-dev-env/blob/master/bench/sysc/src/OrpsocMain.cpp | 09:16 |
| stekern | so yes, you should remove it, but you don't generate it like that | 09:17 |
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| olofk | _franck_: Take a look at the or1200-generic system. It's a verilator test bench in there | 09:49 |
| olofk | https://github.com/openrisc/orpsoc-cores/blob/master/systems/or1200-generic/bench/verilator/tb.cpp | 09:50 |
| olofk | _franck_: You should let verilator take care of the VCD generation too | 09:53 |
| _franck_ | olofk: I was asking myself: if you have models or other IP you want to connect to orpsoc_top where should it be ? | 09:54 |
| _franck_ | you need a verilog testbench top + a cpp top ? | 09:54 |
| olofk | Yes | 09:55 |
| olofk | That's a bit of a pain, but you need to create two different test benches | 09:55 |
| _franck_ | ok, got it | 09:55 |
| olofk | And verilator doesn't handle behavioural HDL code, so I'm not sure that you will be able to run jtag_vpi in verilator | 09:55 |
| stekern | ah, I see olofk is actually doing the clock like that | 09:56 |
| olofk | For example, the task gen_clk in jtag_vpi.v will probably not work | 09:56 |
| stekern | the other way is sc specific I guess? | 09:57 |
| olofk | stekern: Yep. I wanted to avoid the sc deps if possible | 09:58 |
| _franck_ | I won't go with sc | 09:59 |
| olofk | The verilator tb in orpsocv3 doesn't have all the features from orpsocv2. I will need to rewrite some stuff to make things work first | 09:59 |
| _franck_ | olofk: "verilator doesn't handle behavioural HDL code" I've forgotten that one | 10:00 |
| olofk | Yeah, I know. It's a bit problematic. It prevents me from using my wb_bfm_memory model in orpsoc if I want to run through verilator | 10:02 |
| olofk | I hate verilog-mode | 10:18 |
| stekern | I hate verilog-modes default indentation, most other things I like about it | 10:39 |
| olofk | That's more to the point | 10:40 |
| olofk | The missing support for constant user functions in Icarus starts to annoy me quite a bit | 10:53 |
| stekern | what's that? | 10:57 |
| olofk | Like setting the value of a parameter from the return value of a function | 10:58 |
| olofk | When the function inputs are also parameters | 10:58 |
| stekern | ah, yes, but is that limited to icarus? | 10:59 |
| stekern | or yes, now I get what you mean | 10:59 |
| olofk | It's a known issue in icarus | 10:59 |
| stekern | I'd like to use parameters as ifdef's, that's what I was thinking about | 10:59 |
| stekern | but you can't change a parameter depending on another parameters value | 11:00 |
| stekern | I guess you could do that with what you described though | 11:01 |
| stekern | (apart from Icarus, I mean) | 11:01 |
| olofk | I think you should be able to do that if you have constant user functions | 11:16 |
| olofk | Pushed some changes to wb_intercon. Updates are required in your top levels | 11:49 |
| stekern | bah, why isn't this stupid uart working! | 12:15 |
| stekern | I have exported the hps uart1 signals to the fpga and put a loopback between rxd and txd, but I get no feedback in minicom... | 12:16 |
| olofk | stekern: Does it work from the ARM? | 12:58 |
| stekern | olofk: what do you mean? | 13:59 |
| stekern | if I route it to the I/O pin? | 14:00 |
| stekern | I don't know if I have access to that | 14:00 |
| stekern | what I'm doing is taking the txd and rxd signal from the arm's second uart and route them to the top level of the qsys system | 14:01 |
| stekern | then in orpsoc, I just connect them together with a wire | 14:02 |
| stekern | so it's basically ARM only functionality | 14:02 |
| stekern | as a side note, it looks like it's intended to be able to do the other way around, route signals from the fpga out to the hps pins, but it is disabled in qsys | 14:14 |
| stekern | hmm, maybe the software have to configure the pin somehow too... | 14:55 |
| stekern | I must say that the documentation regarding the pin multiplexing is very thin | 14:57 |
| stekern | hmmm, the uart is not completely dead at least, connecting the loop signal to a LED I get output on it | 18:45 |
| stekern | when I press buttons in minicom | 18:45 |
| stekern | so something with the rx side... | 18:46 |
| _franck_ | seloger | 19:09 |
| olofk | Does someone need to change passwords now? :) | 19:11 |
| stekern | nah, he's just securing it, so he won't forget it | 19:13 |
| olofk | Ahh.. saving it in the cloud. That's clever | 19:13 |
| _franck_ | no :) www.seloger.com :) looking for an apartment for rent | 19:23 |
| _franck_ | I just sell mine this evening | 19:24 |
| olofk | I sold mine a few weeks ago | 19:24 |
| _franck_ | I'm fear thinking I'll buy a dirty house and I'll have one year of work to get it branc new... | 19:25 |
| stekern | I have never sold an apartment | 19:26 |
| _franck_ | you'll miss me openrisc buddies ;) | 19:26 |
| stekern | haha, tell me about it | 19:26 |
| olofk | _franck_: Yeah, we can't afford to lose you to house renovation :) | 19:26 |
| stekern | I think it'll have the reverse effect | 19:27 |
| stekern | the more you renovate, the more you appreciate some calm nice openrisc hacking | 19:28 |
| _franck_ | stekern: are you speaking of you kitchen ? | 19:28 |
| _franck_ | :) | 19:28 |
| stekern | look at me, I'm in the middle of a kitchen renovation | 19:28 |
| _franck_ | well, we don't have the same wife I suppose... | 19:29 |
| olofk | It would be fun if you did :) | 19:29 |
| _franck_ | hehe | 19:29 |
| _franck_ | sorry *kind* of wife | 19:30 |
| stekern | and it's the kitchen renovation from hell, wrongly measured benches, broken kitchen sinks, cabinets missing | 19:31 |
| stekern | haha, no, not the same, I hope | 19:31 |
| stekern | same *kind*, that I don't know about neither | 19:31 |
| _franck_ | our wife might not have the same personality ? am I good now ?? | 19:32 |
| stekern | mine goes hard with the whip, how's yours? | 19:33 |
| _franck_ | I've got her for 5 horses and 2 cow, so I don't complain that much :) that's a good deal | 19:33 |
| stekern | I got mine for free, it's afterwards it has got expensive... | 19:39 |
| _franck_ | :) | 19:40 |
| _franck_ | olofk: wb_sdram_ctrl has now a dependency on mt48lc16m16a2 but there is no mt48lc16m16a2.core .... | 20:38 |
| olofk | _franck_: errmm... you must be mistaken. I'm sure that there is one | 20:45 |
| _franck_ | olofk: right should have checked before...Why do I have an error ? I need to check | 20:48 |
| _franck_ | I updated my repo | 20:48 |
| _franck_ | arf ! you uploaded it 4 minutes ago !! :) | 20:49 |
| olofk | Sorry about that. Forgot to push it :) | 20:50 |
| _franck_ | I was about to tell you to wait before pushing it. We should export some parameters and convert some defines to parameters | 20:51 |
| olofk | ahh crap. Sorry about that | 20:51 |
| olofk | I would like though to get the original source of that file | 20:52 |
| _franck_ | no problem can be done later | 20:52 |
| _franck_ | good idea, we should find the original and add patches | 20:52 |
| olofk | I've been looking for it on Micron's website, but can't find the correct one | 21:11 |
| _franck_ | orpsoc_tb.sdram0.Bank0 in the mt48.._loader is not a good idea. My be we should duplicate the loader code each time we need it because here we can't change testbench top name neither sdram instance name | 21:19 |
| olofk | Yeah, I'm not sure where that loader code comes from. It could have been a contribution from a former collegaue | 21:23 |
| olofk | Duplicating it on the testbench top sounds like a good option for now | 21:26 |
| olofk | Oh well. Time for bed now | 21:28 |
| _franck_ | http://www.mikrocontroller.net/attachment/70711/mt48lc8m16a2.v | 21:29 |
| _franck_ | looks like the original one | 21:29 |
| stekern | victory! | 22:31 |
| stekern | uart loopback working | 22:31 |
| stekern | ...then I finally can go to bed... | 22:31 |
| --- Log closed Wed Sep 11 00:00:51 2013 | ||
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