IRC logs for #openrisc Tuesday, 2013-09-10

--- Log opened Tue Sep 10 00:00:49 2013
stekernolofk: I came up with simple workaround for adding the .qip file to the project until we support that properly07:11
stekernjust add a 'set_global_assignment -name QIP_FILE ../src/qsys/synthesis/sockit.qip' in a .tcl that is included in tcl_files07:12
stekernin the end... I might just manually instantiate the hps in orpsoc_top.v08:29
stekernlet's see if I need anything else from qsys first though08:30
stekernright now, it's just a AXI<->avalon bridge08:31
stekernwould make more sense for us to have a AXI<->wb bridge ;)08:31
stekernah, there's actually a lot more things going on inside the hps module that is generated as well08:34
stekernso, maybe it's not feasible to do that08:34
_franck_I have some verilator questions09:08
_franck_I have an existing testbench:
_franck_shoul I just remove the clock generation in my exsiting testbench and create a cpp testbench with a clock generation09:09
_franck_like top->clk = !top->clk;09:09
_franck_ top->eval();09:10
_franck_stekern: do you have any verilator testbench of any of your simulated soc to show me ?09:11
stekernhmm.. I have only used the mor1kx-devenv (which is essentially orpsocv2)09:16
stekernbut it's here that stuff is done:
stekernso yes, you should remove it, but you don't generate it like that09:17
-!- Netsplit *.net <-> *.split quits: larks, Amadiro, ysionneau, arokux, blueCmd_, LoneTech, poke53281, poke53282, simoncook, bentley`, (+8 more, use /NETSPLIT to show all of them)09:18
-!- Netsplit over, joins: simoncook, trevorman, jeremybennett, bentley`, mick_laptop, ssvb, enghong, forkG, LoneTech, larks (+8 more)09:21
olofk_franck_: Take a look at the or1200-generic system. It's a verilator test bench in there09:49
olofk_franck_: You should let verilator take care of the VCD generation too09:53
_franck_olofk: I was asking myself: if you have models or other IP you want to connect to orpsoc_top where should it be ?09:54
_franck_you need a verilog testbench top + a cpp top ?09:54
olofkThat's a bit of a pain, but you need to create two different test benches09:55
_franck_ok, got it09:55
olofkAnd verilator doesn't handle behavioural HDL code, so I'm not sure that you will be able to run jtag_vpi in verilator09:55
stekernah, I see olofk is actually doing the clock like that09:56
olofkFor example, the task gen_clk in jtag_vpi.v will probably not work09:56
stekernthe other way is sc specific I guess?09:57
olofkstekern: Yep. I wanted to avoid the sc deps if possible09:58
_franck_I won't go with sc09:59
olofkThe verilator tb in orpsocv3 doesn't have all the features from orpsocv2. I will need to rewrite some stuff to make things work first09:59
_franck_olofk: "verilator doesn't handle behavioural HDL code" I've forgotten that one10:00
olofkYeah, I know. It's a bit problematic. It prevents me from using my wb_bfm_memory model in orpsoc if I want to run through verilator10:02
olofkI hate verilog-mode10:18
stekernI hate verilog-modes default indentation, most other things I like about it10:39
olofkThat's more to the point10:40
olofkThe missing support for constant user functions in Icarus starts to annoy me quite a bit10:53
stekernwhat's that?10:57
olofkLike setting the value of a parameter from the return value of a function10:58
olofkWhen the function inputs are also parameters10:58
stekernah, yes, but is that limited to icarus?10:59
stekernor yes, now I get what you mean10:59
olofkIt's a known issue in icarus10:59
stekernI'd like to use parameters as ifdef's, that's what I was thinking about10:59
stekernbut you can't change a parameter depending on another parameters value11:00
stekernI guess you could do that with what you described though11:01
stekern(apart from Icarus, I mean)11:01
olofkI think you should be able to do that if you have constant user functions11:16
olofkPushed some changes to wb_intercon. Updates are required in your top levels11:49
stekernbah, why isn't this stupid uart working!12:15
stekernI have exported the hps uart1 signals to the fpga and put a loopback between rxd and txd, but I get no feedback in minicom...12:16
olofkstekern: Does it work from the ARM?12:58
stekernolofk: what do you mean?13:59
stekernif I route it to the I/O pin?14:00
stekernI don't know if I have access to that14:00
stekernwhat I'm doing is taking the txd and rxd signal from the arm's second uart and route them to the top level of the qsys system14:01
stekernthen in orpsoc, I just connect them together with a wire14:02
stekernso it's basically ARM only functionality14:02
stekernas a side note, it looks like it's intended to be able to do the other way around, route signals from the fpga out to the hps pins, but it is disabled in qsys14:14
stekernhmm, maybe the software have to configure the pin somehow too...14:55
stekernI must say that the documentation regarding the pin multiplexing is very thin14:57
stekernhmmm, the uart is not completely dead at least, connecting the loop signal to a LED I get output on it18:45
stekernwhen I press buttons in minicom18:45
stekernso something with the rx side...18:46
olofkDoes someone need to change passwords now? :)19:11
stekernnah, he's just securing it, so he won't forget it19:13
olofkAhh.. saving it in the cloud. That's clever19:13
_franck_no :) :) looking for an apartment for rent19:23
_franck_I just sell mine this evening19:24
olofkI sold mine a few weeks ago19:24
_franck_I'm fear thinking I'll buy a dirty house and I'll have one year of work to get it branc new...19:25
stekernI have never sold an apartment19:26
_franck_you'll miss me openrisc buddies ;)19:26
stekernhaha, tell me about it19:26
olofk_franck_: Yeah, we can't afford to lose you to house renovation :)19:26
stekernI think it'll have the reverse effect19:27
stekernthe more you renovate, the more you appreciate some calm nice openrisc hacking19:28
_franck_stekern: are you speaking of you kitchen ?19:28
stekernlook at me, I'm in the middle of a kitchen renovation19:28
_franck_well, we don't have the same wife I suppose...19:29
olofkIt would be fun if you did :)19:29
_franck_sorry *kind* of wife19:30
stekernand it's the kitchen renovation from hell, wrongly measured benches, broken kitchen sinks, cabinets missing19:31
stekernhaha, no, not the same, I hope19:31
stekernsame *kind*, that I don't know about neither19:31
_franck_our wife might not have the same personality ? am I good now ??19:32
stekernmine goes hard with the whip, how's yours?19:33
_franck_I've got her for 5 horses and 2 cow, so I don't complain that much :) that's a good deal19:33
stekernI got mine for free, it's afterwards it has got expensive...19:39
_franck_olofk: wb_sdram_ctrl has now a dependency on mt48lc16m16a2 but there is no mt48lc16m16a2.core ....20:38
olofk_franck_: errmm... you must be mistaken. I'm sure that there is one20:45
_franck_olofk: right should have checked before...Why do I have an error ? I need to check20:48
_franck_I updated my repo20:48
_franck_arf ! you uploaded it 4 minutes ago !! :)20:49
olofkSorry about that. Forgot to push it :)20:50
_franck_I was about to tell you to wait before pushing it. We should export some parameters and convert some defines to parameters20:51
olofkahh crap. Sorry about that20:51
olofkI would like though to get the original source of that file20:52
_franck_no problem can be done later20:52
_franck_good idea, we should find the original and add patches20:52
olofkI've been looking for it on Micron's website, but can't find the correct one21:11
_franck_orpsoc_tb.sdram0.Bank0 in the mt48.._loader is not a good idea. My be we should duplicate the loader code each time we need it because here we can't change testbench top name neither sdram instance name21:19
olofkYeah, I'm not sure where that loader code comes from. It could have been a contribution from a former collegaue21:23
olofkDuplicating it on the testbench top sounds like a good option for now21:26
olofkOh well. Time for bed now21:28
_franck_looks like the original one21:29
stekernuart loopback working22:31
stekern...then I finally can go to bed...22:31
--- Log closed Wed Sep 11 00:00:51 2013

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