| --- Log opened Wed Jul 24 00:00:40 2013 | ||
| stekern | me and my big mouth... walk in the park, yeah right... | 07:22 |
|---|---|---|
| stekern | starting with the dtlb reload, I remembered that there was a couple of things I've been meaning to do in the lsu, and it makes no sense to start hacking in the dtlb reload stuff in there before I've done them | 07:24 |
| stekern | basically I'm going to do a state machine for the external bus accesses, like I have in the fetcher | 07:24 |
| stekern | because those ext_bus accesses are still a bottle neck timing wise | 07:25 |
| stekern | ... and I have a long term plan to move some of the refill logic (the actual bus access) from icache and dcache into those state machines | 07:26 |
| nvmind | hello | 13:38 |
| olofk | nvmind: hi | 14:07 |
| jeremybennett | nvmind: Hi | 14:08 |
| nvmind | do you know how to solve this warning from iverilog? | 14:13 |
| nvmind | warning: timescale for xxxx inherited from another file. | 14:13 |
| nvmind | from my understanding this is due to the fact that I use a timescale.v file that is included everywhere | 14:14 |
| olofk | timescales are a bit messy in verilog | 14:15 |
| nvmind | but minsoc has the same structure and iverilog doesn't complain | 14:15 |
| olofk | If you just want to get rid of the warning, make sure that every file either includes timescale.v, or that you have a `timescale statement as the first line | 14:16 |
| nvmind | the timescale must be the first line in the file? | 14:17 |
| nvmind | mmm it's strange but I get the warning in every file that has the include | 14:24 |
| olofk | Your timescale.v might not have been found, or it could be empty | 14:25 |
| nvmind | I checked compiling with -Mfilelist | 14:31 |
| nvmind | <path-to-the-project>/soc/timescale.v | 14:32 |
| nvmind | is included | 14:32 |
| nvmind | the content is | 14:32 |
| nvmind | `timescale 1ns/1ps | 14:33 |
| nvmind | I have also checked compiling with -E :) | 14:33 |
| nvmind | and the timescale is included correctly | 14:34 |
| olofk | In xxxx? | 14:34 |
| nvmind | yes. | 14:34 |
| nvmind | this is driving me crazy... really :) | 14:35 |
| olofk | hmm.. could it be compile order maybe? I'm thinking that xxxx might be compiled before timescale.v is available | 14:36 |
| nvmind | should it be compiled or just made it available with a +incdir+ directive? | 14:38 |
| nvmind | http://nopaste.info/0866072cdb.html | 14:42 |
| nvmind | this is the project file I use to build the SoC :) | 14:42 |
| nvmind | is it possible that this issue with the timescale is the root cause of this bug: | 14:55 |
| nvmind | I configured or1200 to jump on reset at the address of a rom containing bootcode | 14:56 |
| nvmind | after 1 clock cycle that cyc and stb are asserted from the master interface of the core they become X | 14:58 |
| nvmind | and this breaks my interconnection logic... | 14:59 |
| nvmind | well... I found the error. | 20:53 |
| nvmind | nothing to do with that warning | 20:53 |
| nvmind | good night. | 20:59 |
| hno | stekern, console=uart,... fix just gone into the tty tree, so that problem should soon be no more than a distant memory. | 23:28 |
| hno | only took one retransmission before the patch got picked up. | 23:31 |
| --- Log closed Thu Jul 25 00:00:42 2013 | ||
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