IRC logs for #openrisc Wednesday, 2013-07-24

--- Log opened Wed Jul 24 00:00:40 2013
stekernme and my big mouth... walk in the park, yeah right...07:22
stekernstarting with the dtlb reload, I remembered that there was a couple of things I've been meaning to do in the lsu, and it makes no sense to start hacking in the dtlb reload stuff in there before I've done them07:24
stekernbasically I'm going to do a state machine for the external bus accesses, like I have in the fetcher07:24
stekernbecause those ext_bus accesses are still a bottle neck timing wise07:25
stekern... and I have a long term plan to move some of the refill logic (the actual bus access) from icache and dcache into those state machines07:26
olofknvmind: hi14:07
jeremybennettnvmind: Hi14:08
nvminddo you know how to solve this warning from iverilog?14:13
nvmindwarning: timescale for xxxx inherited from another file.14:13
nvmindfrom my understanding this is due to the fact that I use a timescale.v file that is included everywhere14:14
olofktimescales are a bit messy in verilog14:15
nvmindbut minsoc has the same structure and iverilog doesn't complain14:15
olofkIf you just want to get rid of the warning, make sure that every file either includes timescale.v, or that you have a `timescale statement as the first line14:16
nvmindthe timescale must be the first line in the file?14:17
nvmindmmm it's strange but I get the warning in every file that has the include14:24
olofkYour timescale.v might not have been found, or it could be empty14:25
nvmindI checked compiling with -Mfilelist14:31
nvmindis included14:32
nvmindthe content is14:32
nvmind`timescale 1ns/1ps14:33
nvmindI have also checked compiling with -E :)14:33
nvmindand the timescale is included correctly14:34
olofkIn xxxx?14:34
nvmindthis is driving me crazy... really :)14:35
olofkhmm.. could it be compile order maybe? I'm thinking that xxxx might be compiled before timescale.v is available14:36
nvmindshould it be compiled or just made it available with a +incdir+ directive?14:38
nvmindthis is the project file I use to build the SoC :)14:42
nvmindis it possible that this issue with the timescale is the root cause of this bug:14:55
nvmindI configured or1200 to jump on reset at the address of a rom containing bootcode14:56
nvmindafter 1 clock cycle that cyc and stb are asserted from the master interface of the core they become X14:58
nvmindand this breaks my interconnection logic...14:59
nvmindwell... I found the error.20:53
nvmindnothing to do with that warning20:53
nvmindgood night.20:59
hnostekern, console=uart,... fix just gone into the tty tree, so that problem should soon be no more than a distant memory.23:28
hnoonly took one retransmission before the patch got picked up.23:31
--- Log closed Thu Jul 25 00:00:42 2013

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