| --- Log opened Tue Jul 02 00:00:08 2013 | ||
| stekern | juliusb: I'm playing with creating a mor1kx qsys component, and as an extension of that, I'll need to create a different bus interface (avalon to start with, I might play with AXI later) | 03:24 |
|---|---|---|
| stekern | the problem I'm having is, how should we handle this modularly in the mor1kx.v top level file | 03:25 |
| stekern | ? | 03:25 |
| stekern | since the module decleration obviously changes | 03:25 |
| stekern | the only sane thing that comes right to my mind is to have seperate top level files, but I'm not sure I'm very fond of that... | 03:26 |
| stekern | what can be wrong if the tick timer is not running in or1ksim? | 05:13 |
| stekern | I'm majorly confused | 05:13 |
| stekern | I've confirmed that TTMR = 0xc0000000, so it should be running | 05:14 |
| stekern | but TTCR is not changing value from 0 | 05:14 |
| stekern | oh... if I set TTMR = 0xc0000001 it start running | 05:16 |
| stekern | that's not how it should work... | 05:19 |
| stekern | so, it seems like it doesn't start counting if TTCR[27:0] == TTMR[TP], even if the mode is continues counting | 05:22 |
| stekern | aha! juliusb has already noticed this some time | 05:30 |
| stekern | http://pastie.org/8102281 | 05:30 |
| stekern | hno: I just tested running 3.9 on mor1kx in a verilator simulation, and it boots to a prompt | 08:04 |
| stekern | it's the closest to a "board" I have atm | 08:04 |
| stekern | wonder what happens if I try to run with or1200 instead of mor1kx | 08:05 |
| juliusb | stekern: I vaguely recall that, very odd isn't it | 09:18 |
| juliusb | has anyone seen the new CERN OHL draft? | 09:18 |
| juliusb | it's not clear on whether it's intended to apply to designs in FPGAs | 09:19 |
| juliusb | at least, not to me, I think I'll post abuot it | 09:19 |
| stekern | link? | 09:39 |
| juliusb | http://lists.ohwr.org/sympa/arc/cernohl/2013-07/msg00000.html | 09:52 |
| juliusb | but I like it | 09:53 |
| juliusb | non-reciprocal hardware license, where they are trying to enforce the sharing of the source by classifying it as the "Documentation" | 09:54 |
| juliusb | so you provide that documentation (and a place where it is published on the 'net, I presume) to any licensee of the work, and they must do the same in the event that they distribute a product containing anything made from that documentation | 09:55 |
| juliusb | I was speaking to Andrew Katz after his presentation at the OSHUG in London a few months back and he was of the opinion that this is probably the best way to do it | 09:55 |
| stekern | yeah, I agree, it makes sense | 10:02 |
| stekern | question is if it actually makes sense for rtl | 10:02 |
| stekern | feels like we are in a gray zone that doesn't fit anywhere... | 10:02 |
| stekern | neither hw nor sw | 10:02 |
| juliusb | I think my claim of "if it goes through logic synthesis then it's basically hardware" isn't too bad | 10:04 |
| juliusb | im not sure any software compilation process is like that... | 10:05 |
| * juliusb waits to be corrected... | 10:05 | |
| juliusb | :) | 10:05 |
| stekern | agree | 10:32 |
| stekern | but I'd be reluctant to call verilog code "documentation", but schematics and pcb layouts I happily would call that | 10:32 |
| stekern | yay, after giving some love to the orpsocv2 sysc code or1200 starts booting linux in the verilated model | 10:35 |
| juliusb | :) what'd you have to change? | 10:41 |
| juliusb | I think they're being very liberal with the term documentation, which is the whole point of this approach to licensing | 10:41 |
| stekern | the same stuff I've already done in mor1kx-devenv | 10:42 |
| stekern | including unistd.h (newer gcc requires that for read/write/pipe etc) and avoiding including files that changes name when you change the underlaying .v files | 10:43 |
| stekern | stuff I've intended to do earlier, but not got a real pressing reason to do until now | 10:44 |
| stekern | I needed to increase the wb_ram_b3 to 32MB from 8MB | 10:45 |
| juliusb | ah ok | 10:45 |
| stekern | olofk: which kernel did you boot with icarus btw? | 10:46 |
| stekern | nm, that question is moot | 10:51 |
| stekern | hno: 3.9 on or1200 boots to prompt too in the verilated model (so essantially, simulated orpsoc with onchip RAM) | 10:53 |
| stekern | I'll test on a real board when I get a chance, but what boards do you have (I recall ordb2a being one of them) | 10:54 |
| stekern | ? | 10:54 |
| olofk | stekern: I only have my ordb2a. Had to return my atlys and ordb1 when I quit ORSoC | 12:13 |
| olofk | oh.. and a SoCKit of course | 12:14 |
| olofk | and hopefully I have a paralella board soon | 12:16 |
| stekern | olofk: the question, about the boards were directed to, hno, but thanks for the info anyway ;) | 12:43 |
| stekern | why is this phone inserting sporadic commas? | 12:44 |
| olofk | stekern: Didn't you buy a windows phone ? | 12:44 |
| stekern | never! | 12:45 |
| stekern | ... I got one for free... | 12:45 |
| stekern | well "got", I assume it would face the same destiny as your dev boards if I quit my job | 12:46 |
| stekern | I would probably miss it less though | 12:46 |
| stekern | I'm waiting for the parallella as well btw | 12:47 |
| olofk | jeremybennett: If you have any favours to collect from the Adapteva guys, make sure that they put the large FPGAs on the boards they're sending to stekern and me | 12:53 |
| jeremybennett | olofk: aren't they all the same? | 13:22 |
| olofk | jeremybennett: I'm not sure anymore actually. They said in a newsletter that the got a deal with Xilinx so that they could populate the boards with Zync Z-7020 instead of Z-7010 | 13:45 |
| olofk | And in the reference manual it says that the board _can_ be built with either. That might just be a note though, and all delivered board contain the same FPGA | 13:47 |
| jeremybennett | I would think their manufacturing run will use all the same FPGAs | 13:48 |
| olofk | jeremybennett: You're probably right | 13:50 |
| stekern | juliusb: I'm leaning towards adding seperate ports for each bus interface rather than creating seperate modules | 18:49 |
| stekern | avalon could potentially use the wb signals as is, since they are so similar | 18:50 |
| olofk | systemC doesn't seem to be very compilable | 20:49 |
| olofk | I don't suppose anyone knows a good way to trim \0 values from verilog strings, except for looping through an array? | 21:08 |
| olofk | That didn't work either. Both $fopen and $sformat seem to need constant arrays | 21:19 |
| olofk | I found a hackish way to trick the verilog string handling. Patch submitted | 22:00 |
| stekern | avalon is as "messy" as wishbone | 22:02 |
| stekern | and time just flies... | 22:04 |
| --- Log closed Wed Jul 03 00:00:10 2013 | ||
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