IRC logs for #openrisc Tuesday, 2013-07-02

--- Log opened Tue Jul 02 00:00:08 2013
stekernjuliusb: I'm playing with creating a mor1kx qsys component, and as an extension of that, I'll need to create a different bus interface (avalon to start with, I might play with AXI later)03:24
stekernthe problem I'm having is, how should we handle this modularly in the mor1kx.v top level file03:25
stekernsince the module decleration obviously changes03:25
stekernthe only sane thing that comes right to my mind is to have seperate top level files, but I'm not sure I'm very fond of that...03:26
stekernwhat can be wrong if the tick timer is not running in or1ksim?05:13
stekernI'm majorly confused05:13
stekernI've confirmed that TTMR = 0xc0000000, so it should be running05:14
stekernbut TTCR is not changing value from 005:14
stekernoh... if I set  TTMR = 0xc0000001 it start running05:16
stekernthat's not how it should work...05:19
stekernso, it seems like it doesn't start counting if TTCR[27:0] == TTMR[TP], even if the mode is continues counting05:22
stekernaha! juliusb has already noticed this some time05:30
stekernhno: I just tested running 3.9 on mor1kx in a verilator simulation, and it boots to a prompt08:04
stekernit's the closest to a "board" I have atm08:04
stekernwonder what happens if I try to run with or1200 instead of mor1kx08:05
juliusbstekern: I vaguely recall that, very odd isn't it09:18
juliusbhas anyone seen the new CERN OHL draft?09:18
juliusbit's not clear on whether it's intended to apply to designs in FPGAs09:19
juliusbat least, not to me, I think I'll post abuot it09:19
juliusbbut I like it09:53
juliusbnon-reciprocal hardware license, where they are trying to enforce the sharing of the source by classifying it as the "Documentation"09:54
juliusbso you provide that documentation (and a place where it is published on the 'net, I presume) to any licensee of the work, and they must do the same in the event that they distribute a product containing anything made from that documentation09:55
juliusbI was speaking to Andrew Katz after his presentation at the OSHUG in London a few months back and he was of the opinion that this is probably the best way to do it09:55
stekernyeah, I agree, it makes sense10:02
stekernquestion is if it actually makes sense for rtl10:02
stekernfeels like we are in a gray zone that doesn't fit anywhere...10:02
stekernneither hw nor sw10:02
juliusbI think my claim of "if it goes through logic synthesis then it's basically hardware" isn't too bad10:04
juliusbim not sure any software compilation process is like that...10:05
* juliusb waits to be corrected...10:05
stekernbut I'd be reluctant to call verilog code "documentation", but schematics and pcb layouts I happily would call that10:32
stekernyay, after giving some love to the orpsocv2 sysc code or1200 starts booting linux in the verilated model10:35
juliusb:) what'd you have to change?10:41
juliusbI think they're being very liberal with the term documentation, which is the whole point of this approach to licensing10:41
stekernthe same stuff I've already done in mor1kx-devenv10:42
stekernincluding unistd.h (newer gcc requires that for read/write/pipe etc) and avoiding including files that changes name when you change the underlaying .v files10:43
stekernstuff I've intended to do earlier, but not got a real pressing reason to do until now10:44
stekernI needed to increase the wb_ram_b3 to 32MB from 8MB10:45
juliusbah ok10:45
stekernolofk: which kernel did you boot with icarus btw?10:46
stekernnm, that question is moot10:51
stekernhno: 3.9 on or1200 boots to prompt too in the verilated model (so essantially, simulated orpsoc with onchip RAM)10:53
stekernI'll test on a real board when I get a chance, but what boards do you have (I recall ordb2a being one of them)10:54
olofkstekern: I only have my ordb2a. Had to return my atlys and ordb1 when I quit ORSoC12:13
olofkoh.. and a SoCKit of course12:14
olofkand hopefully I have a paralella board soon12:16
stekernolofk: the question, about the boards were directed to, hno, but thanks for the info anyway ;)12:43
stekernwhy is this phone inserting sporadic commas?12:44
olofkstekern: Didn't you buy a windows phone ?12:44
stekern... I got one for free...12:45
stekernwell "got", I assume it would face the same destiny as your dev boards if I quit my job12:46
stekernI would probably miss it less though12:46
stekernI'm waiting for the parallella as well btw12:47
olofkjeremybennett: If you have any favours to collect from the Adapteva guys, make sure that they put the large FPGAs on the boards they're sending to stekern and me12:53
jeremybennettolofk: aren't they all the same?13:22
olofkjeremybennett: I'm not sure anymore actually. They said in a newsletter that the got a deal with Xilinx so that they could populate the boards with Zync Z-7020 instead of Z-701013:45
olofkAnd in the reference manual it says that the board _can_ be built with either. That might just be a note though, and all delivered board contain the same FPGA13:47
jeremybennettI would think their manufacturing run will use all the same FPGAs13:48
olofkjeremybennett: You're probably right13:50
stekernjuliusb: I'm leaning towards adding seperate ports for each bus interface rather than creating seperate modules18:49
stekernavalon could potentially use the wb signals as is, since they are so similar18:50
olofksystemC doesn't seem to be very compilable20:49
olofkI don't suppose anyone knows a good way to trim \0 values from verilog strings, except for looping through an array?21:08
olofkThat didn't work either. Both $fopen and $sformat seem to need constant arrays21:19
olofkI found a hackish way to trick the verilog string handling. Patch submitted22:00
stekernavalon is as "messy" as wishbone22:02
stekernand time just flies...22:04
--- Log closed Wed Jul 03 00:00:10 2013

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