IRC logs for #openrisc Saturday, 2013-06-15

--- Log opened Sat Jun 15 00:00:44 2013
stekernI can't read the DRAM from the arm side neither, maybe it's not configured...02:54
stekernjupp, that seems to be it03:52
stekernafter configuring it I can read the DRAM fine from the arm side at least03:52
stekernhno: the AR100 can access the DRAM03:56
stekernthat's pretty cool03:57
stekernso I've got a nice little openrisc board here with a couple of arm co-processor cores ;)03:58
hnostekern, and 2GB of RAM (or is it 1GB?)05:27
hnobut I guess it has no MMU on the OpenRISC side?05:28
stekern2GB of RAM05:34
stekernno, unfortunately no MMU, otherwise we would be able to boot linux on it ;)05:34
stekernbut it has icache (no dcache)05:35
hnoso who is the first to port uClinux to openrisc?05:49
stekernthat's of course an option06:06
stekerntimer is working too06:35
stekernmy crude clk freq detection method shows ~26 MHZ07:22
stekernso, it's probably running of the 24 MHz osc07:22
hnostekern, clock can likely be changed. Haven't seen any hardcoded clock selections in Allwinner chips yet save for SATA and something else...08:53
stekernhno: ok, I'll dig into that some more, I still think my assumption that it runs off the 24 MHz osc as default is valid09:52
stekernanother interesting thing is that it has l.addc support09:52
stekernand a hardware divider10:04
stekernhmm, and it has the mac unit bit set in UPR and l.mac *is* supported10:21
stekernso, this is the current test results:
stekernok, now I've got sun6i u-boot running over the sdcard serial, plan is to boot linux and get ar100 to print out it's stuff on this uart too19:26
hnosounds like a good plan.19:33
--- Log closed Sun Jun 16 00:00:45 2013

Generated by 2.15.2 by Marius Gedminas - find it at!