IRC logs for #openrisc Monday, 2013-06-10

--- Log opened Mon Jun 10 00:00:36 2013
stekernolofk: tomorrow it's time for my arrow workshop09:19
stekernso soon I'm a fullworthy member of the sockittens09:20
olofkstekern: Ahh.. fun. Hope you get some time to play with it. I haven't opened the box since I got it ;(09:44
stekerngetting openrisc running on it is a mandatory task at least09:48
stekerncrosscompiling our toolchains for arm is another, and do some 'standalone' openrisc dev on the board is another09:53
olofkCrosscompiling toolchains for ARM is a great idea.09:57
olofkI was hoping to provide an orpsocv3 port for the FPGA part, but I still haven't fixed the enough-hours-in-a-day bug09:58
stekernI use the 'sleep-less' workaround for that09:59
stekernbut it's not really a long time solution09:59
olofkjuliusb: You know what would be fun to present at OHS. A bus pirate ported to OpenRISC and running on a DE0-Nano10:03
olofkI tried sleep-less mode tonight, powered by my 6-week noise generator. My system doesn't run very stable today.10:05
LoneTechI've heard shortened sleep cycles can be effective, but with my lack of control of when I manage to sleep I can't say it's firsthand10:19
stekernI usually sleep 4-6 hours a night for a month, followed by a week of ~8 hours of nights10:28
stekernolofk: I can comfort you with that the sleep interruptor you have acquired will work for at least 7 years more10:30
stekernI'm teaching mine Java right now10:36
stekernbecause he says he "want to make games" for his phone10:37
stekernwe got a small math app going yesterday, throwing random math questions of the type "5 + 13 ="10:38
olofkLoneTech: Yeah, I think I would find it hard to control my sleep cycles too10:40
olofkstekern: Can't you convince him that all games are actually coded in verilog?10:40
stekernwell, we start in the upper layers, if he hasn't been able to create a full system from scratch to run his games on within a year, I will be *very* dissapointed! =P10:42
olofkDoes anyone know some clever way to get unbuffered reads from stdin in verilog? $fgetc('h8000_0000) seems to be line buffered. At least in modelsim10:52
olofkWithout using VPI, I should add10:53
stekernfinally, they found my sdcard adapter12:29
olofkstekern: Have you tried the tablet at all, or are you just waiting for the tools you need to violate it?12:58
stekernolofk: using stuff for what it is intended for, what's the fun in that?15:22
stekernI've watched some tv-series in the bed on it15:23
stekernthe kids are playing on it a lot15:23
stekernit's pretty handy having around in the kitchen, when you want to quickly check something15:25
--- Log closed Tue Jun 11 00:00:38 2013

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