IRC logs for #openrisc Tuesday, 2013-05-07

--- Log opened Tue May 07 00:00:47 2013
stekernjuliusb: to get zero branch overhead without delay slot, wouldn't you need to do the branch address calculation in fetch stage?03:16
stekernwithout branch prediction03:18
stekernyou would even need branch target prediction to avoid doing the branch address calculation there03:19
stekernI'm still planning on adding simple branch prediction to cappuccino, I don't think there's another way to get any decent fmax out of it without crippling all b(n)f branches to be 2 cycle03:21
stekernor more correctly, crippling all l.sfxx; l.b(n)f to be 3-cycle03:22
stekernI'm not sure what scheme would be best though, initially I thought about a "traditional" backward branches taken forward not03:24
stekernbut I'm playing with the idea of just using the old flag value and recheck in execute stage if it was a misprediction03:25
stekernbecause, for loops, I think that would work pretty well, basically the first jump is potentially a misprediction and the last is a misprediction03:27
stekernfor conditional statements it's a bit of coin tossing, but so is the backwards-taken-forward-not03:28
stekernanother benefit of using the old value is that the compiler can be taught to avoid branch mispredictions (by inserting instructions between the l.sfxx and the l.b(n)f)03:30
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 8084d90 Stefan Kristiansson: cappuccino/cpu: remove unused execute_opc_insn_i AUTOTEMPLATE signal05:34
mor1kxmor1kx/master c3e2bff Stefan Kristiansson: execute_alu: remove unused opc_insn_i signal05:34
--- Log closed Wed May 08 00:00:49 2013

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