IRC logs for #openrisc Sunday, 2013-04-07

--- Log opened Sun Apr 07 00:00:04 2013
andresjkstekern, are you there?06:57
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 7b7dda1 Stefan Kristiansson: cappuccino/ctrl_execute: rename exec_ to execute_07:17
mor1kxmor1kx/master 3a4629f Stefan Kristiansson: cappuccino: resolve branches in decode stage...07:17
andresjkhey! hope you are doing well. I was wondering if you have ideas of peripherals that are needed in the community? I need to develop a peripheral wishbone-compatible to be used as a demonstrative application for OR design-flow for my thesis.07:20
andresjk However I have some requirement:07:20
andresjk1) It must be demonstrative07:20
andresjk2) It must be complex enough to publish a paper in a IEEE conference.07:20
andresjk3) It must be data and processing intensive07:20
andresjk4) It would be cool if It actually helps the community07:20
andresjkI was going into the image processing field, I don't know07:23
andresjkwhat would you say, stekern07:24
stekernyeah, image/audio processing was what came to my mind first too07:24
andresjkI like DSP in general07:25
stekernI still have my long term plan of building a or1k based synthesizer07:25
stekernother stuff keeps pushing it further into the future though...07:26
andresjkoh, really? I suppose you have play with dynamic partial reconfiguration?07:26
andresjksoftware that can synthesized hw and placed in the same SoC07:26
andresjkat demand07:26
stekernumm, I meant an audio synthesizer ;)07:28
andresjkoh, more like an instrument or more like a text-to-speech synthesizer?07:31
stekernyes, instrument07:31
andresjkthat would be cool07:32
andresjkany project with images or video processing?07:34
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 7df2ea3 Stefan Kristiansson: cappuccino/fetch: remove unused delay_slot wire...09:34
mor1kxmor1kx/master b77d0f1 Stefan Kristiansson: cappuccino/fetch: rename fetch_branch_taken_o to fetch_exception_taken_o...09:34
stekernhi rfajardo13:19
rfajardoWhat has been going on? I've heard about an MMU for the new CPU13:27
stekernyup, that among many other things13:29
stekernin the toolchain department we've recently got gdb support in the development toolchain (_franck_), and eglibc port have been initiated (blueCmd)13:33
rfajardoNice :)13:35
rfajardoWhat do you mean by gdb support in the development toolchain? I thought we had gdb support.13:35
stekernyes, in the stable toolchain (or32), that has been brought up to date to the development toolchain (or1k)13:39
rfajardonow I get it13:44
rfajardodid most of the development go away from opencores directly?13:44
rfajardoare you going to join the discussion today evening?13:46
stekernisn't it next sunday?13:51
stekernregarding moving away from opencores, the github organisation was created to bring together the already existing, but scattered projects in private repos on github13:59
stekernmost seem to prefer that worklflow, I don't see a reason to force developers to bend over backwards to do their stuff, there are certainly a shortage of contributors even without that14:01
stekernwe are however keeping documentation and stuff like that at
stekernso there is a 1 point entry for users14:02
stekernthat our wikipages would need a serious overhaul to be more clear, that is an other issue ;)14:03
@juliusbrfajardo: hiya! the teleconf is _next_ sunday14:24
@juliusbstekern: I still couldn't figure out how to get GDB to build14:29
rfajardoI don't have any opinion on what is best, I really only wanted to know. :)14:29
@juliusbis changing --disable-gdb to --enable-gdb all you did?14:29
rfajardojuliusb, heyas, I don't know why I thought it would be this weekend, but I will note it then.14:29
@juliusbI foudn it was looking for some libgui thing, and i found something which said you need to add --disable-gdbtk to stop that occuring14:29
@juliusbrfajardo: nice :) will be good to have you join in14:30
@juliusb(gdb build thing) but then that caused another error later on14:30
@juliusbso I'm still not sure what is really going on..... I suspect maybe there's other flags required?14:30
rfajardobtw, I wasn't able to send to the mailing list. I sent an email to the admin or owner. But I didnt get a reply yet.14:31
@juliusboh yes I saw that email14:34
@juliusb(I get admain emails)14:34
@juliusbbut I don't know what to do14:34
@juliusboh maybe I do14:35
@juliusbone tick....14:35
@juliusbyeah, strange...14:36
@juliusbyou shuold subscribe14:36
@juliusb(I checked in the backend, though, there's nothing sitting there - not sure if jonas already dealt with it or added you or something14:37
@juliusbyeah, I dunno14:37
@juliusbI can't say right now14:37
rfajardoI get the emails, I only can't post.14:48
rfajardoShould I try to subscribe?14:48
stekernjuliusb: yeah, just enable-gdb, I think I only did it in the second stage though, if that make a difference14:49
stekernkeyboard-uart suppot are already in the sysc uart btw, it's just a matter of turning a define on14:50
@juliusbstekern: ah right, I'll try it with second stage then15:34
@juliusb(uart) oh cool, maybe I did that?15:34
@juliusb... and forgot about it? :P15:34
@juliusbno I recall getting u-boot working with it15:34
@juliusbthat's right15:34
@juliusbdid you stil have --disable-sim?15:36
stekernyes, still have --disable-sim15:47
stekern(uart) it's nice, I've got top running in the cyc accurate simulator, and I can reproduce a bug that I've seen in hw15:48
@juliusbhmm it fails trying to link -lsim with that15:48
@juliusbawesome :)15:48
@juliusbhow long's the boot in cycle accurate?15:49
rfajardoDo you have a model from the CPU? This isnt the architectural simulator or the Verilator output, is it?16:01
_franck_juliusb: if you enable sim, you must have or1ksim installed, see the log here:
_franck_or you can use the CGEN sim (like it's describeed  in the log)16:01
@juliusb_franck_: Ah OK, I think I tried --enable-sim and --without-or1ksim, not --disable-or1ksim16:04
@juliusbthat's very confusing, actually, to enable or1ksim you should have --with-or1ksim but to disable it you should use --disable-or1ksim, not --without-or1ksim :P16:05
@juliusbrfajardo: what do you mean?16:05
rfajardoI am wondering what are the models you are simulating.16:06
@juliusbthe RTL, turned into a cycle-accurate SystemC model by verilator16:07
rfajardoagh nice, that was my question16:07
_franck_juliusb: it was clear when I worked on it :) or1ksim is the default. So you can either disable it or use it with-or1ksim=PATH16:08
_franck_but you're right it's not that clear16:08
@juliusbah right16:08
@juliusbif this works i'll document it on the wiki16:08
_franck_ok great, I didn't wnat to do it until someone else has tried it16:09
_franck_I have some more work to do on gdb but I'm working on something else right now...16:10
@juliusbcool, no worries _franck_ 16:10
_franck_I did a complete rewrite of our openocd port. Need to push it on openrisc github but it is so rewrote that I need to push a v2, not just some patches16:11
_franck_I was waiting for some of the parts I wrote to be included in the openOCD mainstream but it not moving at all overthere16:12
stekernjuliusb: around 15 mins I think to get a login prompt16:13
_franck_"The Zurich-based Tages Anzeiger said the politician presented a "bogus tax certificate" to the *Julius Baer* bank."16:16
_franck_Julius Baer bank :) it that a typo ? :)16:16
@juliusb_franck_: on great, what did you change/fix in the OpenOCD port?16:17
_franck_it support adv_debug_sys and mohor interface switching at run time (no need to recompile)16:18
_franck_it generate target description file (xml) and send it to gdb16:18
_franck_so you can add registers without recompile gdb or openocd16:18
_franck_see my configuration file for example:
@juliusbhaha I like the Julius Baer bank, i should bank with them16:23
@juliusb_franck_: awesome stuff on OpenOCD mate!!16:24
@juliusbhow solid is it?16:24
_franck_it is quite good16:24
_franck_see the log here:
_franck_that what you get on gdb16:25
_franck_however, you only got this in gdb when openOCD send the tdesc file. I have to but this file into gdb to have a builtin default tdesc file16:25
@juliusbok nice16:31
rfajardoGuys, I'm looking forward to the teleconference. Have a nice sunday evening!16:50
rfajardoSee you!16:50
stekernjuliusb: will something break if I remove the 'cycle_end' logic on the "CLASSIC" bus_if?17:57
@juliusbnot sure.....17:57
@juliusbhave you tried?17:58
stekernI know it will not break cappuccino17:59
stekernwishbone wise all is kosher without it18:00
@juliusbah right18:01
stekernwell, *shouldn't* break cappuccino18:03
stekernit passes the tests without it too18:04
@juliusbwhy do you want to remove it?18:15
@juliusbI think it's required for the cache-less ones18:18
stekernjust to save 1 cycle, but if it's needed I'll let it be18:21
stekernlooks like I've broke something else... nothing seems to work on de0-nano anymore18:31
@juliusbI think for the slower guys it's needed?18:34
@juliusbI can double check...18:34
@juliusbprontoespresso seems happy enough...18:46
stekernfound what is broken18:53
stekernbut I did that change to fix a thing that breaks in simulations...18:56
stekernare the espressos also happy if the CLASSIC interface is used for ibus and without that?19:00
@juliusbno they need the bursting thing19:06
@juliusbit's handy because they can do some sort of single-cycle execution19:06
@juliusbpronto was fine with that change BTW19:07
@juliusblooking at espresso now19:07
stekernah, ok19:07
stekernI get a 1.46->1.50 increase in dhrystone without it19:08
stekernand 92.32->92.60 in coremark19:09
@juliusbcool, fair enough19:10
@juliusbis bus behaviour correct, though?19:10
stekernshould be, it's fine to assert cyc&stb in the cycle after an ack19:11
stekernaccording to the wb spec at least19:11
@juliusbespresso appears OK19:11
@juliusbI say ditch it19:11
@juliusb(un an unrelated note, pronto+tcm is broken for some reason ... on the mor1kx-version test)19:12
* juliusb investigates19:12
stekernis that a new regression?19:13
* stekern hides19:13
@juliusbI'm not sure to be honest - I'm fairly certain this passed all tests recently19:14
@juliusbI didn't look closely enough. The cycle end guy is in the classic interface bit?19:16
@juliusbyep - the cycle_end change breaks it....19:17
@juliusbso the TCM thing is kind of different - I don't use the mor1kx top wrapper - instead I've instantiated the CPU and the ibus goes directly to a single-cycle access memory19:17
@juliusbthe dbus goes through the usual bus interface19:17
@juliusbso, oddly, pronto with TCM relies on those accesses taking longer?!19:18
@juliusbyep! they do19:18
@juliusbI should fix that19:18
stekernsounds like some corner case that falls out when things speed up19:18
@juliusbso pronto doesn't suffer, but tcm pronto does19:18
stekernI'm planning on adding the 'dual function' bus_if soonish anyway, so no panic removing it19:21
@juliusb'dual function'?19:22
@juliusbone which does bursting for caches for both instructino and data?19:22
stekernyes, just a mix between the single cycle and read burst if, with a 'cpu_burst_i' signal to control the bursting runtime19:24
stekernyou could of course just add it to the readburst if, but I thought about doing a third interface, because you can shave off some logic that's not needed then19:26
stekernI had planned on doing that tonight, but looks like it's bughunting weather19:28
@juliusbyeah, a third interface sounds good19:35
stekerncan you guess in what module the bug I'm hunting is in?19:37
@juliusbhaha, I can't really but, um, at a guess - caches?19:39
stekernno, it's my nemesis, fetch...19:40
@juliusbme too19:42
@juliusbthis bug is to do with the TCM fetch unit19:42
stekernthis is basically about figuring out which access is going on when an exception comes19:43
@juliusbbecause storing is faster now (takes only 2 cycles), if we have a few in a row, we get padv_i to fetch going 0101010119:43
@juliusband the instruction fetch for some reason thinks it should keep going19:43
@juliusbso they get out of sync19:44
@juliusband we skip an instruction19:44
stekernI think I've figured out what's going on on my side, I just realised that the pipeline_flush comes one cycle before the branch signal on exceptions, but at the same cycle as rfe20:25
stekernyay! taking that info into account and I've got something that works both on the board and simulation20:31
@juliusboh yeah, subtle differences like that will catch one out every time :-/20:31
mor1kx[mor1kx] skristiansson pushed 2 new commits to master:
mor1kxmor1kx/master 959c24e Stefan Kristiansson: bus_if_wb32: whitespace cleanup20:54
mor1kxmor1kx/master cef0162 Stefan Kristiansson: cappuccino/fetch: always flush on incoming exception...20:54
stekernhmm, is it possible to download a patch of a commit from github?20:57
@juliusbquite probably20:58
stekernI'd like steal your de0-nano fix over to my orpsocv2 repo20:59
@juliusbah right21:00
@juliusbwhich fix?21:01
@juliusbbeware I've switched the core to prontoespresso21:01
@juliusbI probably should have kept it as cappuccino, truth be told21:01
@juliusbsorry about that21:01
@juliusbthere's a bunch of really annoying corner cases in the fetch unit now that the LSU is quicker :P21:03
@juliusbdamn progress21:04
stekernthe wb arbiter fix21:07
stekernbecause I suspect I've exeperienced some of that on the board(s)21:07
@juliusbok cool21:10
@juliusbok cool21:12
@juliusbwhoops, up and enter in the wrong window...21:13
stekernseems more stable now, a bit of a performance hit though21:31
@juliusbgrrr, I can't get the TCM bug fixed21:32
@juliusbwill require a signal into the ctrl I think21:32
@juliusbleaving it alone for this evening I think21:32
@juliusbwill get the chiphack stuff working first21:32
stekernmmm, bed is calling here21:33
@juliusbis a good idea. night21:37
--- Log closed Mon Apr 08 00:00:06 2013

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