| --- Log opened Sun Apr 07 00:00:04 2013 | ||
| andresjk | stekern, are you there? | 06:57 |
|---|---|---|
| stekern | yep | 07:11 |
| mor1kx | [mor1kx] skristiansson pushed 2 new commits to master: https://github.com/openrisc/mor1kx/compare/001f4fd7d9c5...3a4629ff46fc | 07:17 |
| mor1kx | mor1kx/master 7b7dda1 Stefan Kristiansson: cappuccino/ctrl_execute: rename exec_ to execute_ | 07:17 |
| mor1kx | mor1kx/master 3a4629f Stefan Kristiansson: cappuccino: resolve branches in decode stage... | 07:17 |
| andresjk | hey! hope you are doing well. I was wondering if you have ideas of peripherals that are needed in the community? I need to develop a peripheral wishbone-compatible to be used as a demonstrative application for OR design-flow for my thesis. | 07:20 |
| andresjk | However I have some requirement: | 07:20 |
| andresjk | 1) It must be demonstrative | 07:20 |
| andresjk | 2) It must be complex enough to publish a paper in a IEEE conference. | 07:20 |
| andresjk | 3) It must be data and processing intensive | 07:20 |
| andresjk | 4) It would be cool if It actually helps the community | 07:20 |
| andresjk | I was going into the image processing field, I don't know | 07:23 |
| andresjk | what would you say, stekern | 07:24 |
| stekern | yeah, image/audio processing was what came to my mind first too | 07:24 |
| andresjk | I like DSP in general | 07:25 |
| stekern | I still have my long term plan of building a or1k based synthesizer | 07:25 |
| stekern | other stuff keeps pushing it further into the future though... | 07:26 |
| andresjk | oh, really? I suppose you have play with dynamic partial reconfiguration? | 07:26 |
| andresjk | software that can synthesized hw and placed in the same SoC | 07:26 |
| andresjk | at demand | 07:26 |
| stekern | umm, I meant an audio synthesizer ;) | 07:28 |
| andresjk | oh, more like an instrument or more like a text-to-speech synthesizer? | 07:31 |
| stekern | yes, instrument | 07:31 |
| andresjk | that would be cool | 07:32 |
| andresjk | any project with images or video processing? | 07:34 |
| mor1kx | [mor1kx] skristiansson pushed 2 new commits to master: https://github.com/openrisc/mor1kx/compare/3a4629ff46fc...b77d0f1905d1 | 09:34 |
| mor1kx | mor1kx/master 7df2ea3 Stefan Kristiansson: cappuccino/fetch: remove unused delay_slot wire... | 09:34 |
| mor1kx | mor1kx/master b77d0f1 Stefan Kristiansson: cappuccino/fetch: rename fetch_branch_taken_o to fetch_exception_taken_o... | 09:34 |
| rfajardo | Hello | 13:05 |
| stekern | hi rfajardo | 13:19 |
| rfajardo | What has been going on? I've heard about an MMU for the new CPU | 13:27 |
| stekern | yup, that among many other things | 13:29 |
| stekern | in the toolchain department we've recently got gdb support in the development toolchain (_franck_), and eglibc port have been initiated (blueCmd) | 13:33 |
| rfajardo | Nice :) | 13:35 |
| rfajardo | What do you mean by gdb support in the development toolchain? I thought we had gdb support. | 13:35 |
| stekern | yes, in the stable toolchain (or32), that has been brought up to date to the development toolchain (or1k) | 13:39 |
| stekern | github.com/openrisc/or1k-src | 13:39 |
| rfajardo | ahhh | 13:44 |
| rfajardo | now I get it | 13:44 |
| rfajardo | did most of the development go away from opencores directly? | 13:44 |
| rfajardo | are you going to join the discussion today evening? | 13:46 |
| stekern | isn't it next sunday? | 13:51 |
| stekern | regarding moving away from opencores, the github organisation was created to bring together the already existing, but scattered projects in private repos on github | 13:59 |
| stekern | most seem to prefer that worklflow, I don't see a reason to force developers to bend over backwards to do their stuff, there are certainly a shortage of contributors even without that | 14:01 |
| stekern | we are however keeping documentation and stuff like that at opencores.org/or1k | 14:01 |
| stekern | so there is a 1 point entry for users | 14:02 |
| stekern | that our wikipages would need a serious overhaul to be more clear, that is an other issue ;) | 14:03 |
| @juliusb | rfajardo: hiya! the teleconf is _next_ sunday | 14:24 |
| @juliusb | stekern: I still couldn't figure out how to get GDB to build | 14:29 |
| rfajardo | I don't have any opinion on what is best, I really only wanted to know. :) | 14:29 |
| @juliusb | is changing --disable-gdb to --enable-gdb all you did? | 14:29 |
| rfajardo | juliusb, heyas, I don't know why I thought it would be this weekend, but I will note it then. | 14:29 |
| @juliusb | I foudn it was looking for some libgui thing, and i found something which said you need to add --disable-gdbtk to stop that occuring | 14:29 |
| @juliusb | rfajardo: nice :) will be good to have you join in | 14:30 |
| @juliusb | (gdb build thing) but then that caused another error later on | 14:30 |
| @juliusb | so I'm still not sure what is really going on..... I suspect maybe there's other flags required? | 14:30 |
| rfajardo | btw, I wasn't able to send to the mailing list. I sent an email to the admin or owner. But I didnt get a reply yet. | 14:31 |
| @juliusb | oh yes I saw that email | 14:34 |
| @juliusb | (I get openrisc.net admain emails) | 14:34 |
| @juliusb | but I don't know what to do | 14:34 |
| @juliusb | oh maybe I do | 14:35 |
| @juliusb | one tick.... | 14:35 |
| @juliusb | yeah, strange... | 14:36 |
| @juliusb | you shuold subscribe | 14:36 |
| @juliusb | (I checked in the backend, though, there's nothing sitting there - not sure if jonas already dealt with it or added you or something | 14:37 |
| @juliusb | yeah, I dunno | 14:37 |
| @juliusb | I can't say right now | 14:37 |
| rfajardo | hehe | 14:47 |
| rfajardo | I get the emails, I only can't post. | 14:48 |
| rfajardo | Should I try to subscribe? | 14:48 |
| stekern | juliusb: yeah, just enable-gdb, I think I only did it in the second stage though, if that make a difference | 14:49 |
| stekern | keyboard-uart suppot are already in the sysc uart btw, it's just a matter of turning a define on | 14:50 |
| @juliusb | stekern: ah right, I'll try it with second stage then | 15:34 |
| @juliusb | (uart) oh cool, maybe I did that? | 15:34 |
| @juliusb | ... and forgot about it? :P | 15:34 |
| @juliusb | no I recall getting u-boot working with it | 15:34 |
| @juliusb | that's right | 15:34 |
| @juliusb | did you stil have --disable-sim? | 15:36 |
| stekern | yes, still have --disable-sim | 15:47 |
| stekern | (uart) it's nice, I've got top running in the cyc accurate simulator, and I can reproduce a bug that I've seen in hw | 15:48 |
| @juliusb | hmm it fails trying to link -lsim with that | 15:48 |
| @juliusb | awesome :) | 15:48 |
| @juliusb | how long's the boot in cycle accurate? | 15:49 |
| rfajardo | Do you have a model from the CPU? This isnt the architectural simulator or the Verilator output, is it? | 16:01 |
| _franck_ | juliusb: if you enable sim, you must have or1ksim installed, see the log here: https://github.com/openrisc/or1k-src/commit/3cce57ef9830f8efede13e02198d29479ec8aa03 | 16:01 |
| _franck_ | or you can use the CGEN sim (like it's describeed in the log) | 16:01 |
| @juliusb | _franck_: Ah OK, I think I tried --enable-sim and --without-or1ksim, not --disable-or1ksim | 16:04 |
| @juliusb | that's very confusing, actually, to enable or1ksim you should have --with-or1ksim but to disable it you should use --disable-or1ksim, not --without-or1ksim :P | 16:05 |
| @juliusb | rfajardo: what do you mean? | 16:05 |
| rfajardo | I am wondering what are the models you are simulating. | 16:06 |
| @juliusb | the RTL, turned into a cycle-accurate SystemC model by verilator | 16:07 |
| rfajardo | agh nice, that was my question | 16:07 |
| _franck_ | juliusb: it was clear when I worked on it :) or1ksim is the default. So you can either disable it or use it with-or1ksim=PATH | 16:08 |
| _franck_ | but you're right it's not that clear | 16:08 |
| @juliusb | ah right | 16:08 |
| @juliusb | if this works i'll document it on the wiki | 16:08 |
| _franck_ | ok great, I didn't wnat to do it until someone else has tried it | 16:09 |
| _franck_ | I have some more work to do on gdb but I'm working on something else right now... | 16:10 |
| @juliusb | cool, no worries _franck_ | 16:10 |
| _franck_ | I did a complete rewrite of our openocd port. Need to push it on openrisc github but it is so rewrote that I need to push a v2, not just some patches | 16:11 |
| _franck_ | I was waiting for some of the parts I wrote to be included in the openOCD mainstream but it not moving at all overthere | 16:12 |
| stekern | juliusb: around 15 mins I think to get a login prompt | 16:13 |
| _franck_ | juliusb: http://www.globalpost.com/dispatch/news/afp/130406/disgraced-french-budget-minister-lied-swiss-bank | 16:16 |
| _franck_ | "The Zurich-based Tages Anzeiger said the politician presented a "bogus tax certificate" to the *Julius Baer* bank." | 16:16 |
| _franck_ | Julius Baer bank :) it that a typo ? :) | 16:16 |
| @juliusb | _franck_: on great, what did you change/fix in the OpenOCD port? | 16:17 |
| _franck_ | it support adv_debug_sys and mohor interface switching at run time (no need to recompile) | 16:18 |
| _franck_ | it generate target description file (xml) and send it to gdb | 16:18 |
| _franck_ | so you can add registers without recompile gdb or openocd | 16:18 |
| _franck_ | see my configuration file for example: https://github.com/Franck79/openOCD/blob/auto_tdesc/or1k_olimex_mohor.tcl | 16:19 |
| @juliusb | haha I like the Julius Baer bank, i should bank with them | 16:23 |
| @juliusb | _franck_: awesome stuff on OpenOCD mate!! | 16:24 |
| @juliusb | how solid is it? | 16:24 |
| _franck_ | it is quite good | 16:24 |
| @juliusb | cool | 16:24 |
| _franck_ | see the log here: https://github.com/openrisc/or1k-src/commit/943c7d500654a312bf64c90935d2d1b93f2a9e90 | 16:24 |
| _franck_ | that what you get on gdb | 16:25 |
| _franck_ | however, you only got this in gdb when openOCD send the tdesc file. I have to but this file into gdb to have a builtin default tdesc file | 16:25 |
| @juliusb | ok nice | 16:31 |
| rfajardo | Guys, I'm looking forward to the teleconference. Have a nice sunday evening! | 16:50 |
| rfajardo | See you! | 16:50 |
| stekern | juliusb: will something break if I remove the 'cycle_end' logic on the "CLASSIC" bus_if? | 17:57 |
| @juliusb | not sure..... | 17:57 |
| @juliusb | have you tried? | 17:58 |
| stekern | I know it will not break cappuccino | 17:59 |
| stekern | wishbone wise all is kosher without it | 18:00 |
| @juliusb | ah right | 18:01 |
| stekern | well, *shouldn't* break cappuccino | 18:03 |
| stekern | =P | 18:03 |
| stekern | it passes the tests without it too | 18:04 |
| @juliusb | why do you want to remove it? | 18:15 |
| @juliusb | I think it's required for the cache-less ones | 18:18 |
| stekern | just to save 1 cycle, but if it's needed I'll let it be | 18:21 |
| stekern | looks like I've broke something else... nothing seems to work on de0-nano anymore | 18:31 |
| @juliusb | I think for the slower guys it's needed? | 18:34 |
| @juliusb | I can double check... | 18:34 |
| @juliusb | s | 18:41 |
| @juliusb | s/s// | 18:42 |
| @juliusb | prontoespresso seems happy enough... | 18:46 |
| stekern | found what is broken | 18:53 |
| stekern | but I did that change to fix a thing that breaks in simulations... | 18:56 |
| stekern | are the espressos also happy if the CLASSIC interface is used for ibus and without that? | 19:00 |
| @juliusb | no they need the bursting thing | 19:06 |
| @juliusb | it's handy because they can do some sort of single-cycle execution | 19:06 |
| @juliusb | pronto was fine with that change BTW | 19:07 |
| @juliusb | looking at espresso now | 19:07 |
| stekern | ah, ok | 19:07 |
| stekern | I get a 1.46->1.50 increase in dhrystone without it | 19:08 |
| stekern | and 92.32->92.60 in coremark | 19:09 |
| @juliusb | cool, fair enough | 19:10 |
| @juliusb | is bus behaviour correct, though? | 19:10 |
| stekern | should be, it's fine to assert cyc&stb in the cycle after an ack | 19:11 |
| stekern | according to the wb spec at least | 19:11 |
| @juliusb | espresso appears OK | 19:11 |
| @juliusb | I say ditch it | 19:11 |
| @juliusb | (un an unrelated note, pronto+tcm is broken for some reason ... on the mor1kx-version test) | 19:12 |
| * juliusb investigates | 19:12 | |
| stekern | is that a new regression? | 19:13 |
| * stekern hides | 19:13 | |
| @juliusb | haha | 19:14 |
| @juliusb | I'm not sure to be honest - I'm fairly certain this passed all tests recently | 19:14 |
| @juliusb | ah-ha! | 19:15 |
| @juliusb | I didn't look closely enough. The cycle end guy is in the classic interface bit? | 19:16 |
| stekern | yep | 19:16 |
| @juliusb | yep - the cycle_end change breaks it.... | 19:17 |
| @juliusb | so the TCM thing is kind of different - I don't use the mor1kx top wrapper - instead I've instantiated the CPU and the ibus goes directly to a single-cycle access memory | 19:17 |
| @juliusb | the dbus goes through the usual bus interface | 19:17 |
| @juliusb | so, oddly, pronto with TCM relies on those accesses taking longer?! | 19:18 |
| @juliusb | yep! they do | 19:18 |
| @juliusb | I should fix that | 19:18 |
| stekern | sounds like some corner case that falls out when things speed up | 19:18 |
| @juliusb | so pronto doesn't suffer, but tcm pronto does | 19:18 |
| stekern | I'm planning on adding the 'dual function' bus_if soonish anyway, so no panic removing it | 19:21 |
| @juliusb | 'dual function'? | 19:22 |
| @juliusb | one which does bursting for caches for both instructino and data? | 19:22 |
| stekern | yes, just a mix between the single cycle and read burst if, with a 'cpu_burst_i' signal to control the bursting runtime | 19:24 |
| stekern | you could of course just add it to the readburst if, but I thought about doing a third interface, because you can shave off some logic that's not needed then | 19:26 |
| stekern | I had planned on doing that tonight, but looks like it's bughunting weather | 19:28 |
| @juliusb | yeah, a third interface sounds good | 19:35 |
| stekern | can you guess in what module the bug I'm hunting is in? | 19:37 |
| @juliusb | haha, I can't really but, um, at a guess - caches? | 19:39 |
| stekern | no, it's my nemesis, fetch... | 19:40 |
| @juliusb | :) | 19:42 |
| @juliusb | me too | 19:42 |
| @juliusb | this bug is to do with the TCM fetch unit | 19:42 |
| stekern | this is basically about figuring out which access is going on when an exception comes | 19:43 |
| @juliusb | because storing is faster now (takes only 2 cycles), if we have a few in a row, we get padv_i to fetch going 01010101 | 19:43 |
| @juliusb | and the instruction fetch for some reason thinks it should keep going | 19:43 |
| @juliusb | so they get out of sync | 19:44 |
| @juliusb | and we skip an instruction | 19:44 |
| stekern | I think I've figured out what's going on on my side, I just realised that the pipeline_flush comes one cycle before the branch signal on exceptions, but at the same cycle as rfe | 20:25 |
| stekern | yay! taking that info into account and I've got something that works both on the board and simulation | 20:31 |
| @juliusb | oh yeah, subtle differences like that will catch one out every time :-/ | 20:31 |
| @juliusb | sweet! | 20:32 |
| mor1kx | [mor1kx] skristiansson pushed 2 new commits to master: https://github.com/openrisc/mor1kx/compare/b77d0f1905d1...cef016242731 | 20:54 |
| mor1kx | mor1kx/master 959c24e Stefan Kristiansson: bus_if_wb32: whitespace cleanup | 20:54 |
| mor1kx | mor1kx/master cef0162 Stefan Kristiansson: cappuccino/fetch: always flush on incoming exception... | 20:54 |
| stekern | hmm, is it possible to download a patch of a commit from github? | 20:57 |
| @juliusb | quite probably | 20:58 |
| stekern | I'd like steal your de0-nano fix over to my orpsocv2 repo | 20:59 |
| @juliusb | ah right | 21:00 |
| @juliusb | which fix? | 21:01 |
| @juliusb | beware I've switched the core to prontoespresso | 21:01 |
| @juliusb | I probably should have kept it as cappuccino, truth be told | 21:01 |
| @juliusb | sorry about that | 21:01 |
| @juliusb | there | 21:03 |
| @juliusb | there's a bunch of really annoying corner cases in the fetch unit now that the LSU is quicker :P | 21:03 |
| @juliusb | damn progress | 21:04 |
| stekern | the wb arbiter fix | 21:07 |
| stekern | because I suspect I've exeperienced some of that on the board(s) | 21:07 |
| @juliusb | ok cool | 21:10 |
| @juliusb | ok cool | 21:12 |
| @juliusb | whoops, up and enter in the wrong window... | 21:13 |
| stekern | seems more stable now, a bit of a performance hit though | 21:31 |
| @juliusb | grrr, I can't get the TCM bug fixed | 21:32 |
| @juliusb | will require a signal into the ctrl I think | 21:32 |
| @juliusb | leaving it alone for this evening I think | 21:32 |
| @juliusb | will get the chiphack stuff working first | 21:32 |
| stekern | mmm, bed is calling here | 21:33 |
| @juliusb | is a good idea. night | 21:37 |
| --- Log closed Mon Apr 08 00:00:06 2013 | ||
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