juliusb | _franck_: right you are, I've never done it but care is taken with that sort of thing AFAIK | 01:33 |
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stekern_ | juliusb: that sounds good to me | 09:36 |
-!- You're now known as stekern | 09:36 | |
* stekern is back in cold finland :( | 09:36 | |
ams | stekern: finland rocks | 10:09 |
stekern | ams: yeah, nothing wrong with the country, it's the climate I'm complaining about ;) | 10:23 |
juliusb | stekern: cool, I'll push stuff at some point soon. I have software breakpoints working for espresso and pronto espresso | 11:55 |
juliusb | and all the carry/overflow stuff | 11:55 |
juliusb | (but that's already in there) | 11:55 |
juliusb | i'm wondering if you want me to try and put in the software breakpoint stuff in the cappuccino? | 11:56 |
jeremybennett | juliusb: I'm curious - I thought software breakpoints were independent of the architectural implementation? | 11:57 |
juliusb | I'm still waiting for the ASIC companies to pop up on east coast Australia, perferrably north of the Queensland/NSW border :) Then I'm over there at the drop of a hat | 11:57 |
juliusb | jeremybennett: what do you mean by "architectural implementation"? | 11:57 |
jeremybennett | I mean that I thought GDB just wrote the trap instruction, and that was the same on all OR1K implementations. | 11:58 |
juliusb | unfortunately in Australia, the only ASIC they know is the Australian Securities and Investments Comission | 11:58 |
juliusb | jeremybennett: yes, but you stil need to set DSR[TE] and have DRR[TE] asserted when the trap occurs and double check all of the stalling occurs correctly etc | 11:59 |
jeremybennett | You mean you are not enjoying this fine British weather. The best cold drizzle in the world here today. | 11:59 |
juliusb | that functionality wasn't in the mor1kx yet | 11:59 |
jeremybennett | Ah - that's in GDB terms hardware breakpoints. | 11:59 |
juliusb | I'm talking about the mor1kx here, by the way. | 11:59 |
jeremybennett | software breakpoints is where you replace the instruction with l.trap and catch the interrupt that results. | 12:00 |
juliusb | I'm talking about software breakpoints - GDB inserts a l.trap in the place where it wants to break, saving the original instruction | 12:00 |
juliusb | but for that to cause the processor to stall you still need a bit of fancy stuff in the processor RTL | 12:00 |
jeremybennett | Ah - I get you. This is bare metal, so you don't have an interrupt handler. | 12:00 |
juliusb | I guess so? | 12:01 |
jeremybennett | You could make it work without the debug unit, but only with a minimal RTOS to pick up the interrupt. | 12:01 |
juliusb | if you hit a l.trap without this stuff in, you vector to 0xe00 | 12:01 |
jeremybennett | I've been working on gdbserver for Linux for the last few weeks, so my mindset is elsewhere. | 12:01 |
juliusb | ah right :) | 12:01 |
jeremybennett | You could have a handler at 0xe00, but then you would not be truly bare metal. Like a RTOS version of gdbserver I suppose. | 12:01 |
juliusb | I'm talking making sure GDB's software breakpoint stuff works, because it's handy, and we have no hardware breakpoint support at the moment | 12:01 |
jeremybennett | That's good. | 12:02 |
juliusb | sure, that's a possibility, but this is for baremetal, I guess, as you said. | 12:02 |
jeremybennett | Always exciting debugging the debugger. | 12:02 |
juliusb | :) | 12:02 |
juliusb | That's one thign which _must_ work | 12:02 |
stekern | juliusb: feel free to give adding it to cappuccino a try | 12:12 |
stekern | atm debugging is completely broken in my working tree | 12:13 |
stekern | I'll sort that out later when things are remotely stable otherwise ;) | 12:13 |
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