IRC logs for #openrisc Saturday, 2013-02-23

blueCmdams: hello15:52
stekernhmm, why does alignment exception have a higher priority than dtlb miss?16:38
stekernI mean, if the address that came out of the dmmu is invalid, why should the alignment of that override the dtlb miss?16:39
juliusbmmm, it's possible for the address which comes out of the DMMU to be invalid?16:40
stekernwell, "invalid" as in not valid in the context16:42
stekernotoh, the alignment come from the lower bits16:44
stekernso what's in the dtlb shouldn't matter16:44
juliusbah yes16:45
juliusbof course you're just getting the upper physical address bits out of the DTLB, so really it's the initial address which is generated which will cause the exception16:46
juliusbin which case it makes sense that the alignment error should be triggered before any lookup error16:46
stekernbut one problem remains, what should the alignment exception handler do with ear?16:47
stekernaah, it should be virtual ea16:47
stekernso, yes, I agre16:48
juliusbyou mean the address reported for the exception?16:48
juliusbyep, virtual makes sense16:49
stekernwonder if that's what happens in mor1kx...16:49
stekernbut that's not the problem now, I'm getting a alignment and a dtlb miss at the same time, but the address should be aligned16:49
juliusbmmm well I guess you gate the DTLB lookup if an alignment exception has been flagged?16:52
stekernnah, but the alignment exception have higher priority in cappuccino_ctrl16:53
juliusbwell, I made sure those priorities were right16:53
juliusbwell, I hadn't put in the MMU ones though, you did that I guess :)16:54
stekernyup, and I think I've got those right too16:54
stekernand the alignment exception is taken16:54
stekernso it's probably right16:54
serp_what do I need to do to make the toolchain build on a ubuntu system?16:57
stekernmy problem is that c000b860 of this code is causing the alignment exception17:12
juliusbyeah that's odd17:17
stekernbut my first thought that the dtlb miss happening at the same time was clearly wrong17:18
stekernneed to gather some more info ;)17:18
stekerncontrolling my de0-nano on the other side of the globe through vnc is a bit slow though ;)17:19
juliusbhaha hardcore17:20
juliusbi got given a de0 nano on Thursday by Jeremy17:20
juliusbgoing to use it for the OSHUG FPGA workshop we're preparing for in late April17:20
juliusbnever used one, keen to check it out, so may be using your flow sometime soon17:20
stekernit's a neat board, has everything one needs except uart converter and ethernet17:23
stekernand the altera tools are nice17:25
juliusbit does seem nice17:26
juliusbI like my nexys3 though :)17:26
juliusband my google nexus 417:26
juliusbi want all things to be named nex*17:26
stekernI really should replace my n900 with something17:28
stekernI want a faster n900 with a larger screen...17:28
serp_hmm the instructions on don't work17:48
_franck_what's going wrong ?17:50
_franck_are you building the "old" or32 toolchain (not the devlopment or1k toolchain) ?17:57
serp_no idea17:57
serp_I build the one from  git://
_franck_this is where you should start17:58
serp_ok thanks18:00
serp_is not the official website of openrisc?18:11
_franck_well it's a long story. However, most recent articles can be found at
andresjk_franck_, can the Xilinx MIG DDR2 controller support 4 masters? Right now the verilog module says it supports 3 masters which are already used by the eth the d_mc and i_mc but there is no comment on scalability20:39
andresjkthe data arbiter supports 2 masters but are used already by the or1200 and the debugger20:40
andresjkand no comments on scalability also20:41
_franck_you only have to uncomment more ports22:30
_franck_oups sorry you've already read this and told me there is only two master port22:32
_franck_if you want to have one more master, you can chain arbiters so master1 and master2 are connected to arbiter122:34
_franck_slave port of arbiter 1 is connected to the first master port of arbiter222:35
_franck_the second port of arbiter 2 is connected to master322:35
_franck_andresjk: I don't know about the Xilinx MIG DDR2 controller22:36
andresjkit makes senses but if the arbiter1 output/slave is connected to master1 of arbiter2. Arbiter1 will never be able to request the bus. Only the master3 which is connected to arbiter2 could request a peripheral connected to master1 or 2 since arbiter1 is a slave.23:09
andresjkohh I think "default slave for chaning" answers my doubt23:12

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