| ams | hi | 14:16 |
|---|---|---|
| blueCmd | ams: hello | 15:52 |
| stekern | hmm, why does alignment exception have a higher priority than dtlb miss? | 16:38 |
| stekern | I mean, if the address that came out of the dmmu is invalid, why should the alignment of that override the dtlb miss? | 16:39 |
| juliusb | mmm, it's possible for the address which comes out of the DMMU to be invalid? | 16:40 |
| stekern | well, "invalid" as in not valid in the context | 16:42 |
| stekern | otoh, the alignment come from the lower bits | 16:44 |
| stekern | so what's in the dtlb shouldn't matter | 16:44 |
| juliusb | ah yes | 16:45 |
| juliusb | of course you're just getting the upper physical address bits out of the DTLB, so really it's the initial address which is generated which will cause the exception | 16:46 |
| juliusb | in which case it makes sense that the alignment error should be triggered before any lookup error | 16:46 |
| stekern | but one problem remains, what should the alignment exception handler do with ear? | 16:47 |
| stekern | aah, it should be virtual ea | 16:47 |
| stekern | so, yes, I agre | 16:48 |
| stekern | e | 16:48 |
| juliusb | you mean the address reported for the exception? | 16:48 |
| stekern | yes | 16:49 |
| juliusb | yep, virtual makes sense | 16:49 |
| stekern | wonder if that's what happens in mor1kx... | 16:49 |
| juliusb | hehe | 16:49 |
| stekern | but that's not the problem now, I'm getting a alignment and a dtlb miss at the same time, but the address should be aligned | 16:49 |
| juliusb | mmm well I guess you gate the DTLB lookup if an alignment exception has been flagged? | 16:52 |
| stekern | nah, but the alignment exception have higher priority in cappuccino_ctrl | 16:53 |
| juliusb | well, I made sure those priorities were right | 16:53 |
| juliusb | well, I hadn't put in the MMU ones though, you did that I guess :) | 16:54 |
| stekern | yup, and I think I've got those right too | 16:54 |
| stekern | and the alignment exception is taken | 16:54 |
| stekern | so it's probably right | 16:54 |
| serp_ | what do I need to do to make the toolchain build on a ubuntu system? | 16:57 |
| juliusb | http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Prerequisites | 16:58 |
| serp_ | thanks | 16:59 |
| stekern | my problem is that c000b860 of this code http://pastie.org/6322314 is causing the alignment exception | 17:12 |
| juliusb | yeah that's odd | 17:17 |
| stekern | but my first thought that the dtlb miss happening at the same time was clearly wrong | 17:18 |
| stekern | need to gather some more info ;) | 17:18 |
| stekern | controlling my de0-nano on the other side of the globe through vnc is a bit slow though ;) | 17:19 |
| juliusb | haha hardcore | 17:20 |
| juliusb | i got given a de0 nano on Thursday by Jeremy | 17:20 |
| juliusb | going to use it for the OSHUG FPGA workshop we're preparing for in late April | 17:20 |
| juliusb | never used one, keen to check it out, so may be using your flow sometime soon | 17:20 |
| stekern | it's a neat board, has everything one needs except uart converter and ethernet | 17:23 |
| stekern | and the altera tools are nice | 17:25 |
| juliusb | it does seem nice | 17:26 |
| juliusb | I like my nexys3 though :) | 17:26 |
| juliusb | and my google nexus 4 | 17:26 |
| juliusb | i want all things to be named nex* | 17:26 |
| stekern | I really should replace my n900 with something | 17:28 |
| stekern | I want a faster n900 with a larger screen... | 17:28 |
| juliusb | :) | 17:28 |
| serp_ | hmm the instructions on http://openrisc.net/toolchain-build.html don't work | 17:48 |
| _franck_ | what's going wrong ? | 17:50 |
| serp_ | http://007be1448e36737d.paste.se/ | 17:54 |
| _franck_ | are you building the "old" or32 toolchain (not the devlopment or1k toolchain) ? | 17:57 |
| serp_ | no idea | 17:57 |
| serp_ | I build the one from git://openrisc.net/jonas/toolchain | 17:57 |
| _franck_ | http://opencores.org/or1k/OpenRISC_GNU_tool_chain | 17:58 |
| _franck_ | this is where you should start | 17:58 |
| serp_ | ok thanks | 18:00 |
| serp_ | is openrisc.net not the official website of openrisc? | 18:11 |
| _franck_ | well it's a long story. However, most recent articles can be found at http://opencores.org/or1k/ | 18:13 |
| andresjk | _franck_, can the Xilinx MIG DDR2 controller support 4 masters? Right now the verilog module says it supports 3 masters which are already used by the eth the d_mc and i_mc but there is no comment on scalability | 20:39 |
| andresjk | the data arbiter supports 2 masters but are used already by the or1200 and the debugger | 20:40 |
| andresjk | and no comments on scalability also | 20:41 |
| _franck_ | https://github.com/Franck79/orpsocv2/blob/master/boards/altera/de1/rtl/verilog/arbiter/arbiter_dbus.v | 22:29 |
| _franck_ | you only have to uncomment more ports | 22:30 |
| _franck_ | oups sorry you've already read this and told me there is only two master port | 22:32 |
| _franck_ | if you want to have one more master, you can chain arbiters so master1 and master2 are connected to arbiter1 | 22:34 |
| _franck_ | slave port of arbiter 1 is connected to the first master port of arbiter2 | 22:35 |
| _franck_ | the second port of arbiter 2 is connected to master3 | 22:35 |
| _franck_ | andresjk: I don't know about the Xilinx MIG DDR2 controller | 22:36 |
| andresjk | it makes senses but if the arbiter1 output/slave is connected to master1 of arbiter2. Arbiter1 will never be able to request the bus. Only the master3 which is connected to arbiter2 could request a peripheral connected to master1 or 2 since arbiter1 is a slave. | 23:09 |
| andresjk | ohh I think "default slave for chaning" answers my doubt | 23:12 |
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