IRC logs for #openrisc Tuesday, 2013-01-08

stekernunder Linux, can several different virtual addresses map into one physical address?09:11
Xarkstekern: I would sure think so (e.g. with a read only mapping).09:20
stekernXark: hmm, bummer... can you give a more concrete example?09:26
stekernI'm asking because I want to know what countermeasures are needed to handle aliasing with a virtually indexed, physically tagged cache09:28
XarkYeah.  I assume you have purused this (but doesn't seem to go into too much detail) ->
stekernhmm, yes, but it was a while since I read that, thanks for reminding me about that document09:31
Xarkstekern: Besides it "making sense". Here is some good indirect evidence that multiple virtual addresses can map to a single physical address (when counting "used" memory) ->
XarkAlso consider the case of multiple processes "mmap"'ing a shared writable page (so probably not read only).09:31
XarkOf course, different CPUs have to deal with cache coherence different ways (on some systems, cache will be flushed when MMU is remapped, e.g.).09:32
stekernmmm, I kind of suspected that it would be the case09:43
* Xark notes he is just starting to look into openrisc (and FPGA and soft-cores in general) so is not really familiar with openrisc MMU specifics (hopefully a bit improved over MIPS).09:56
stekernI haven't looked at MIPS MMU, what are the problems there?09:58
stekernI'm currently implementing MMUs for mor1kx (
stekernand as always, I know nothing when I start, and am happily learning during the journey ;)09:59
Xarkstekern: Well, I am not sure of the specifics, but I believe it was very expensive CPU wise to manage the MMU (and I think required a slow remapping between task switches).10:00
Xark  ... but not too much detail.10:01
stekernyeah, software TLB refill10:03
XarkI think the overhead of that TLB refill exception is what I am thinking of (some MIPS systems I worked on had an "identity mapping" on the MMU so they never needed to deal with the >10% overhead - or something painful).10:03
stekernor1200 does that too10:03
stekernand the first incarnation of the MMUs I'm working too as well10:03
XarkAlso depends how big TLB cache is (it was "too small" on some MIPS chips).10:03
stekernbut I'd like to do hardware walking in the future10:03
stekernthe openrisc architecture supports 4 ways x 128 entries10:08
stekerniirc, or1200 have 1 way x 6410:09
Xarkstekern: That is the TLB or the cache?10:10
XarkThe (older) MIPS R4000ish system I am thinking of had (looks like) 48x1.10:11
blueCmdstekern: had any time to run my patches through that regression thing of yours?22:18

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