IRC logs for #openrisc Monday, 2012-12-31

ErantYeah, turns out it was a misconfigured clock feedback.05:11
stekernErant: nice that you figured it out ;)05:12
ErantIt wasn't pretty.05:12
ErantIt would work for like 3-4 synthesis runs, and then stop. And sometimes a make clean would fix it, sometimes a small change would fix it, etc.05:13
stekernthat kind of bugs are the worst :(05:13
ErantYurp. Oh well, now I just gotta figure out why I can't get much more than like 40MHz out of the or1k core.05:17
ErantI'm getting some async set/reset warnings for the Spartan6, maybe that has something to do with it.05:18
ErantActually, I say 40MHz, that constraint just failed timing.05:20
ErantMaybe 30MHz05:21
ErantEuh. Weird. The critical path is through the debug unit05:39
stekernhow fast does the jtag clk go?05:40
ErantI constrained it at like 10MHz.05:41
Erant  Source:               onchip_ram_top/ack_we (FF)05:43
Erant  Destination:          or1200_top/or1200_du/dwcr1_8 (FF)05:43
ErantThat's the worst path, but most of the logic is in or1200_du05:43
stekernbut that's wb clock only, right?05:44
stekerni.e. not a transition from jtag clk to wb clock05:44
ErantAt this point I'm trying to get the wb clk up.05:45
ErantI'd like it to run at at least 50MHz, which I think is doable.05:45
stekernyes, I've been running or1200 on atlys at 50 MHz05:45
ErantRight. So. I have a feeling this is because of some patches that minsoc applies to the core.05:46
stekernwhat does that onchip_ram look like?05:46
-!- Netsplit *.net <-> *.split quits: forkG05:47
ErantIt adds watchpoint support to the core, which it looks like is the thing causing the problems05:47
-!- Netsplit over, joins: forkG05:47
stekernah, ok05:47
ErantI'm seeing this priority structure. Lots of chained muxes.05:48
stekernwhat revision of or1200 does minsoc use btw?08:33
_franck_LoneTech: can I take a look at your vjtag generic implementation in openocd ?13:20
stekernhmm, are the xTLBEIR registers optional?15:13
stekernthere is a present bit available for them and at least Linux looks at it and write straight to the dtlb if it's not available15:14
_franck_stekern, blueCmd : I just gie or1k-src a try and this is what I get:15:16
stekernthat of course only works with 1-way tlbs15:16
_franck_could you help me before I start searching ?15:16
stekernon 32-bit machines, you have to configure with --disable-werror15:18
stekernit's in the build instructions for the Linux toolchain here:
stekernI added it to the newlib instructions as well15:20
stekernwe should fix it, but I'm not sure exactly how, those are generated by cgen15:20
_franck_did you just add it in the  Newlib toolchain (or1k-elf) section ?15:22
stekernah, I see now you had som other error there too15:22
stekernbut try with --disable-werror, if the second error is still there after that, then let's investigate15:23
stekernyes, added it now, since I realised it was missing ;)15:23
_franck_I already did. But I'll retry from scratch15:24
stekernyour fix could maybe somehow be added to what that get's generated from15:25
stekernin your second error, it tries to run autogen, don't you have that on your machine?15:27
stekernnot sure why it would need to run that though15:27
stekernbut otoh, autotools have always been black magic to me...15:28
_franck_I though I had it...15:28
_franck_me too, that's why I asked here :)15:28
_franck_however, I was really sure I was using autogen all the time. eg. when compiling openOCD15:29
_franck_ok, it's better after installing autogen (like the message was telling me) ;)15:35
stekernbah, I can't find where that enum get generated from15:36
stekernat least not by quickly grepping15:36
stekernI can't see linux setting the I/DMMUCR anywhere, so to get hardware walking working, that has to be added16:01
stekernmy guess is in switch_mm, but I'm not sure16:01
stekernsetting the pagetable pointer that is16:01
Erantstekern: Euhm. Good question. Lemme check the SVN rev16:08
Erantstekern: 'rel1'?16:09
ErantThat's the tag anyway16:09
LoneTech_franck_: it's an ugly misplaced hack, and would take me some time to dig up (not at work).. hang on16:30
LoneTechmore time than I expected, lost power on that machine16:31
LoneTechoh, and it has not been successfully tested (don't recall if I even tested it after fixing the related ft2232 bug)16:32
stekernErant: That's ~4 years old16:49
stekernI think the hw watchpoint patches only applies to that, but if you don't really need wp support I'd update to tot svn16:51
Erantstekern: That'd probably explain why I just failed timing at 33MHz16:51
ErantMaybe I should give orpsoc another try. I like the minimal implementation of minsoc, but if it's based on an aged design :/16:53
Erantstekern: Actually, turns out that patch is just fixing hardware breakpoint support.17:05
ErantWe'll see how easily I can copy-paste ToT into minsoc.17:06
ErantSeeing as my HDL is still iffy at best.17:06
stekernErant: you can try this repo: git://
stekernI have stuff in there that I haven't got around to push to svn17:10
stekernfor the atlys board17:10
ErantFair enough.17:10
ErantI actually think I may have looked at that.17:12
stekernstill don't understand why the uart didn't work for you17:12
Erantfwiw, I think the wrong part is selected.17:12
ErantYeah, I might go back to that now that I have a better understanding of how everything works17:13
stekernwrong part?17:13
ErantFPGA_PART ?=xc6slx45-2-csg32417:13
ErantI think the part on the Atlys board is a -3 speedgrade17:13
stekernI'm pretty sure it's -2, at least on my rev of the board17:14
stekernwhere did you get the -3 from though?17:27
LoneTech_franck_: it's now at (files with vjtag in their names), but it's at best proof of concept level.17:29
Erantstekern: Hmm. The Atlys circuit board is a complete, ready-to-use digital circuit development platform based on a Xilinx Spartan-6 LX45 FPGA, speed grade -318:17
ErantThat's Rev C though18:17
stekernwell, I have rev C, but I'm certain I have read that it's a -220:29
stekern...and I have a sticker under mine that says -220:30
stekernI bought mine right when it hit the store though, so it's of course possible that they are putting -3s on them now20:31
stekernI could of course be wrong too, but I didn't grasp that number out of thin air, that I'm sure of ;)20:34
stekernOk, on the schematic I got with my board it says: IC11B XC6SLX45-2CSG324C20:35
stekernand no reference to speed grade in the reference manual20:36
Erantstekern: Weird. The online reference manual says -3.20:36
ErantAnyway, minsoc doesn't seem to mind ToT or1200.20:36
stekernbut it's a small thing for you to change if you're certain your board is -320:36
stekernonly for the better ;)20:36
ErantOh, sure.20:36
ErantIs minsoc still being actively supported?20:37
stekernRaul Fajardo (rfajardo) seems to answer stuff on the forums now and then, was a while since I saw him on irc though21:42
ErantFair enough. The SoC really benefits from ToT or120021:56
ErantI just met timing at 50MHz, while I couldn't hit 33MHz with the rel121:56
ErantEven though it doesn't seem to actually work.22:01
ErantLet's try the -2 speed grade, maybe it really is a -222:04
Erantstekern: You might be right. I just synthed it at -2 (Had to go down to 45MHz) and then it worked...23:02
ErantMaybe I just have excessive jitter. I dunno.23:09
ErantI'll stick to -2, it's not like I needed that 5MHz.23:09
--- Log closed Tue Jan 01 00:46:24 2013
--- Log opened Tue Jan 01 00:46:40 2013
-!- Irssi: #openrisc: Total of 17 nicks [0 ops, 0 halfops, 0 voices, 17 normal]00:46
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_franck_LoneTech: thanks10:29

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