| Erant | Yeah, turns out it was a misconfigured clock feedback. | 05:11 |
|---|---|---|
| stekern | Erant: nice that you figured it out ;) | 05:12 |
| Erant | It wasn't pretty. | 05:12 |
| Erant | It would work for like 3-4 synthesis runs, and then stop. And sometimes a make clean would fix it, sometimes a small change would fix it, etc. | 05:13 |
| stekern | that kind of bugs are the worst :( | 05:13 |
| Erant | Yurp. Oh well, now I just gotta figure out why I can't get much more than like 40MHz out of the or1k core. | 05:17 |
| Erant | I'm getting some async set/reset warnings for the Spartan6, maybe that has something to do with it. | 05:18 |
| Erant | Actually, I say 40MHz, that constraint just failed timing. | 05:20 |
| Erant | Maybe 30MHz | 05:21 |
| Erant | Euh. Weird. The critical path is through the debug unit | 05:39 |
| stekern | how fast does the jtag clk go? | 05:40 |
| Erant | I constrained it at like 10MHz. | 05:41 |
| Erant | Source: onchip_ram_top/ack_we (FF) | 05:43 |
| Erant | Destination: or1200_top/or1200_du/dwcr1_8 (FF) | 05:43 |
| Erant | That's the worst path, but most of the logic is in or1200_du | 05:43 |
| stekern | but that's wb clock only, right? | 05:44 |
| stekern | i.e. not a transition from jtag clk to wb clock | 05:44 |
| Erant | Right. | 05:44 |
| Erant | At this point I'm trying to get the wb clk up. | 05:45 |
| Erant | I'd like it to run at at least 50MHz, which I think is doable. | 05:45 |
| stekern | yes, I've been running or1200 on atlys at 50 MHz | 05:45 |
| Erant | Right. So. I have a feeling this is because of some patches that minsoc applies to the core. | 05:46 |
| stekern | what does that onchip_ram look like? | 05:46 |
| -!- Netsplit *.net <-> *.split quits: forkG | 05:47 | |
| Erant | It adds watchpoint support to the core, which it looks like is the thing causing the problems | 05:47 |
| -!- Netsplit over, joins: forkG | 05:47 | |
| stekern | ah, ok | 05:47 |
| Erant | I'm seeing this priority structure. Lots of chained muxes. | 05:48 |
| stekern | what revision of or1200 does minsoc use btw? | 08:33 |
| _franck_ | LoneTech: can I take a look at your vjtag generic implementation in openocd ? | 13:20 |
| stekern | hmm, are the xTLBEIR registers optional? | 15:13 |
| stekern | there is a present bit available for them and at least Linux looks at it and write straight to the dtlb if it's not available | 15:14 |
| _franck_ | stekern, blueCmd : I just gie or1k-src a try and this is what I get: | 15:16 |
| _franck_ | http://pastie.org/5602120 | 15:16 |
| stekern | that of course only works with 1-way tlbs | 15:16 |
| _franck_ | could you help me before I start searching ? | 15:16 |
| stekern | on 32-bit machines, you have to configure with --disable-werror | 15:18 |
| stekern | it's in the build instructions for the Linux toolchain here: http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Installation_of_development_versions | 15:20 |
| stekern | I added it to the newlib instructions as well | 15:20 |
| stekern | we should fix it, but I'm not sure exactly how, those are generated by cgen | 15:20 |
| _franck_ | did you just add it in the Newlib toolchain (or1k-elf) section ? | 15:22 |
| _franck_ | :) | 15:22 |
| stekern | ah, I see now you had som other error there too | 15:22 |
| _franck_ | yes | 15:23 |
| stekern | but try with --disable-werror, if the second error is still there after that, then let's investigate | 15:23 |
| stekern | yes, added it now, since I realised it was missing ;) | 15:23 |
| _franck_ | I already did. But I'll retry from scratch | 15:24 |
| stekern | your fix could maybe somehow be added to what that get's generated from | 15:25 |
| stekern | in your second error, it tries to run autogen, don't you have that on your machine? | 15:27 |
| stekern | not sure why it would need to run that though | 15:27 |
| stekern | but otoh, autotools have always been black magic to me... | 15:28 |
| _franck_ | I though I had it... | 15:28 |
| _franck_ | me too, that's why I asked here :) | 15:28 |
| _franck_ | however, I was really sure I was using autogen all the time. eg. when compiling openOCD | 15:29 |
| _franck_ | ok, it's better after installing autogen (like the message was telling me) ;) | 15:35 |
| stekern | bah, I can't find where that enum get generated from | 15:36 |
| stekern | at least not by quickly grepping | 15:36 |
| stekern | I can't see linux setting the I/DMMUCR anywhere, so to get hardware walking working, that has to be added | 16:01 |
| stekern | my guess is in switch_mm, but I'm not sure | 16:01 |
| stekern | setting the pagetable pointer that is | 16:01 |
| Erant | stekern: Euhm. Good question. Lemme check the SVN rev | 16:08 |
| Erant | stekern: 'rel1'? | 16:09 |
| Erant | That's the tag anyway | 16:09 |
| LoneTech | _franck_: it's an ugly misplaced hack, and would take me some time to dig up (not at work).. hang on | 16:30 |
| LoneTech | more time than I expected, lost power on that machine | 16:31 |
| LoneTech | oh, and it has not been successfully tested (don't recall if I even tested it after fixing the related ft2232 bug) | 16:32 |
| stekern | Erant: That's ~4 years old | 16:49 |
| stekern | I think the hw watchpoint patches only applies to that, but if you don't really need wp support I'd update to tot svn | 16:51 |
| Erant | stekern: That'd probably explain why I just failed timing at 33MHz | 16:51 |
| Erant | Maybe I should give orpsoc another try. I like the minimal implementation of minsoc, but if it's based on an aged design :/ | 16:53 |
| Erant | stekern: Actually, turns out that patch is just fixing hardware breakpoint support. | 17:05 |
| Erant | We'll see how easily I can copy-paste ToT into minsoc. | 17:06 |
| Erant | Seeing as my HDL is still iffy at best. | 17:06 |
| stekern | Erant: you can try this repo: git://git.openrisc.net/stefan/orpsoc | 17:09 |
| stekern | I have stuff in there that I haven't got around to push to svn | 17:10 |
| stekern | for the atlys board | 17:10 |
| Erant | Fair enough. | 17:10 |
| Erant | I actually think I may have looked at that. | 17:12 |
| stekern | still don't understand why the uart didn't work for you | 17:12 |
| Erant | fwiw, I think the wrong part is selected. | 17:12 |
| Erant | Yeah, I might go back to that now that I have a better understanding of how everything works | 17:13 |
| stekern | wrong part? | 17:13 |
| Erant | FPGA_PART ?=xc6slx45-2-csg324 | 17:13 |
| Erant | I think the part on the Atlys board is a -3 speedgrade | 17:13 |
| stekern | I'm pretty sure it's -2, at least on my rev of the board | 17:14 |
| stekern | where did you get the -3 from though? | 17:27 |
| LoneTech | _franck_: it's now at http://donkey.vernier.se/~yann/openrisc-public/ (files with vjtag in their names), but it's at best proof of concept level. | 17:29 |
| LoneTech | gtg | 17:31 |
| Erant | stekern: Hmm. The Atlys circuit board is a complete, ready-to-use digital circuit development platform based on a Xilinx Spartan-6 LX45 FPGA, speed grade -3 | 18:17 |
| Erant | That's Rev C though | 18:17 |
| stekern | well, I have rev C, but I'm certain I have read that it's a -2 | 20:29 |
| stekern | ...and I have a sticker under mine that says -2 | 20:30 |
| stekern | I bought mine right when it hit the store though, so it's of course possible that they are putting -3s on them now | 20:31 |
| stekern | I could of course be wrong too, but I didn't grasp that number out of thin air, that I'm sure of ;) | 20:34 |
| stekern | Ok, on the schematic I got with my board it says: IC11B XC6SLX45-2CSG324C | 20:35 |
| stekern | and no reference to speed grade in the reference manual | 20:36 |
| Erant | stekern: Weird. The online reference manual says -3. | 20:36 |
| Erant | Anyway, minsoc doesn't seem to mind ToT or1200. | 20:36 |
| stekern | but it's a small thing for you to change if you're certain your board is -3 | 20:36 |
| stekern | only for the better ;) | 20:36 |
| Erant | Oh, sure. | 20:36 |
| Erant | Is minsoc still being actively supported? | 20:37 |
| stekern | Raul Fajardo (rfajardo) seems to answer stuff on the forums now and then, was a while since I saw him on irc though | 21:42 |
| Erant | Fair enough. The SoC really benefits from ToT or1200 | 21:56 |
| Erant | I just met timing at 50MHz, while I couldn't hit 33MHz with the rel1 | 21:56 |
| Erant | Even though it doesn't seem to actually work. | 22:01 |
| Erant | Let's try the -2 speed grade, maybe it really is a -2 | 22:04 |
| Erant | stekern: You might be right. I just synthed it at -2 (Had to go down to 45MHz) and then it worked... | 23:02 |
| Erant | Maybe I just have excessive jitter. I dunno. | 23:09 |
| Erant | I'll stick to -2, it's not like I needed that 5MHz. | 23:09 |
| --- Log closed Tue Jan 01 00:46:24 2013 | ||
| --- Log opened Tue Jan 01 00:46:40 2013 | ||
| -!- Irssi: #openrisc: Total of 17 nicks [0 ops, 0 halfops, 0 voices, 17 normal] | 00:46 | |
| -!- Irssi: Join to #openrisc was synced in 21 secs | 00:46 | |
| _franck_ | LoneTech: thanks | 10:29 |
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