IRC logs for #openrisc Tuesday, 2012-11-27

--- Log closed Tue Nov 27 06:00:32 2012
--- Log opened Tue Nov 27 06:00:45 2012
-!- Irssi: #openrisc: Total of 20 nicks [1 ops, 0 halfops, 0 voices, 19 normal]06:00
-!- Irssi: Join to #openrisc was synced in 23 secs06:01
stekernbah, this is annoying, I'm trying to run the stuff on real metal, and couldn't even get a simple hello world working10:10
stekernso I threw in a signaltap and now it works...10:10
stekernah, running some other code in between gets it in the same kind of state10:19
@juliusbyeah we need some good reset to launch code, that's always a problem12:00
stekernseeing all kinds of inconsistent behaviour12:51
stekernloads that has 1 bit flipped etc12:51
stekernhmm, u-boot gives some fun info at least12:56
stekernunhandled exception, 0x500 tick timer12:56
stekernit at least prints something ;)13:00
@juliusb:) better than nothing13:13
@juliusbbut i hate that bad behaviour from a newly hacked-together CPU13:14
stekernyeah, you start chasing some bug and when you thought you've almost caught it, if you just could get that extra little piece of information. so you change something to get that and the bug have changed completely...13:45
stekernhmm, are the serial shifters default now?13:45
stekernI'm seeing long stalls on srai and slli13:45
stekernbut I think I see the bug now at least, looks like a hazard bug13:55
stekernrfa_o has the right value during the first cycle of an stall by the fetcher, then it changes to something wrong13:56
@juliusbstekern: good question about the serial shifters. if we had some implementation-specific registers we could put a bit in to indicate what the configuration is and dump it out of the synthesised build to see exactly how it was configured :)14:05
@juliusbI don't think they're default, though, no14:05
@juliusbbarrel should be14:05
stekernI'll check it, could be that it's fetch that just happened to stall at the same time14:07
stekernI'm thinking about the "random" bus access times again14:09
@juliusboh yes14:09
@juliusbfor testing?14:09
stekernit would be really good to have them while running tests14:09
stekernI'm thinking something in the line of: first access 1-cycle delay, second access 2-cycle delay etc14:10
@juliusbsure, it's easy enough to put into the RAM model I believe14:10
stekernit will be deterministic, but probably will shake out bugs14:10
stekernexactly, very simple14:10
@juliusbthat sounds good - my solution uses an LFSR-based delay randomisation14:11
stekernlike, go up to ten cycle delay as max and start over at 014:11
@juliusbprobably another nice feature would be to add built-in latency generation patterns14:11
stekernyou already have an LFSR delay randomizer?14:13
stekernin mor1kx-dev-env?14:15
stekernyes you do14:16
@juliusbjust switch on that parameter, and it should work14:16
@juliusbhaven't fully tested it for a few weeks, I think, though14:16
stekernI really should update my mor1kx-dev-env, shouldn't I?14:17
@juliusbah, the comment on line 327 says "Random ACK negation" which is what it was used for initially14:17
@juliusbbut now it's a random access latency for bursts14:18
@juliusbwell, for any access actually, but all appear to be bursts14:18
@juliusbit would be easy enough to add on another system to add a base delay to that\14:18
stekernthat would shake stuff around a bit14:22
@juliusbyou're running with caches on the whole time, too?14:23
stekernmmm, whenever the caches are enabled14:30
stekerninteresting or1k-shortbranch fails now, while it passed before I updated mor1kx-dev-env14:30
stekernah, but you've done "Lots of additions." to that ;)14:33
@juliusboh yes a lot of additions to the mor1kx-dev-env sw test library :)14:34
@juliusbmore torture for the cores14:34
stekernit's great14:34
stekernI have a little lsu test too14:34
stekernthat cbasic test is good torture, but should really be shopped down to several smaller ones14:36
stekernI noticed it's a pain when that fails14:37
* juliusb agrees14:37
* juliusb got that :)14:37
stekernshopping is for the wife ;)14:37
@juliusbthere's nothing to say she couldn't also refactor cbasic :)14:39
@juliusbI suspect we'd be quicker though14:39
stekernnah, she's really fast14:40
stekern... but sloppy as hell ;)14:40
stekernnice, with the latest hazard fix u-boot boots14:41
stekernspeaking about the wife, I'm pretty proud to say that she's using only open source tools for her profession14:42
stekerngimp, inkscape, libre office etc14:42
@juliusbno way!14:42
@juliusbvery cool14:43
stekernshe even turned down an "intern" since she had no gimp experience, only photoshop ;)14:43
@juliusbhaha, hilarious14:43
@juliusbprobably not for the prospective intern, they'll learn hopefully14:43
stekernsame here14:44

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