IRC logs for #openrisc Monday, 2012-11-19

@juliusb_franck_: regarding the bitbang JTAG driver, yes I believe I had read that somewhere before. I agree, though, it's at a low level however it'd be interesting to see the difference in speed between the to11:44
@juliusbstekern: are you sorting exceptions due to lengthening the pipeline?11:47
@juliusbif so, my sympathies11:47
@juliusbstekern: I'll push some patches soon which factor out the tick timer and PIC11:48
@stekernjuliusb: mmm, and I understand your sympathy ;)11:48
@juliusband, as well, all of the CFGRs11:48
@stekernpush it, push it11:48
@stekernI'm making progress in the early mornings on the pipeline rework, got a pipeline forwarding problem related to exceptions sorted out this morning11:49
@stekerntests up to or1200-simple are passing11:49
@juliusbnice :)11:50
@juliusbso, ok you'll need to hold my hand again11:50
@juliusbi'm ona branch11:50
@juliusbfrom the openrisc/mor1kx repo11:50
@juliusbit's called spr-unit-splitout11:50
@stekernstill haven't pulled your latest mor1kx-devenv with the new tests though11:50
@juliusbto push to openrisc do I just do git push spr-unit-splitout openrisc/masteR?11:50
@stekerngit push openrisc spr-unit-splitout:master11:52
@juliusbhmm OK11:52
@juliusbthat's not obvious :)11:52
@stekernit is ;)11:53
@juliusbok pushing11:53
mor1kx[mor1kx] juliusbaxter pushed 7 new commits to master:
mor1kxmor1kx/master ef17b75 Julius Baxter: cappuccino: put tick timer and PIC in own modules11:53
mor1kxmor1kx/master 5a81a79 Julius Baxter: ctrl_espresso: replace PIC logic with module11:53
mor1kxmor1kx/master 1fa7b5b Julius Baxter: ctrl_espresso: replace tick timer logic with module11:53
@juliusboh no!11:53
@stekernthe syntax is: git push <remote> <src-branch>:<dest-branch>11:53
@juliusbah right OK11:54
@juliusbwhat happened to mr mor1kx?11:54
@stekernhe's a hit'n'runner :)11:55
@juliusbah right :)11:56
@juliusbspeaking of, I'll have to hit you with that patch and run myself, back later11:56
@stekern;) see you11:57
@stekernit's nice cleanup btw12:09
@juliusband everything still works :)12:33
@juliusbso if you update mor1kx-dev-env you'll see 2 new tests, or1k-intloop and or1k-tickloop12:38
@juliusbcappuccino fails one or both, I can't recall, due to the incorrect EPCR being saved12:39
@juliusbit also fails the DSX test, I don't know why12:39
@juliusbnot the same reason I think12:39
@juliusbso on a branch currently the cappuccino deasserts the i'm-in-a-delay-slot signal when the fetch stage takes the new branch target12:40
@stekernyeah, I'll take a look at that when I pass all the other tests12:41
@stekernmight be that it just works then :)12:41
@juliusbbut, if the exception occurs around there (while we're fetching the instruction at the address we're bracnhing to) the EPCR should be the address we're branching to, but instead it takes the address of the delay slot12:41
@stekernbranch target/detection have already got some changes12:41
@juliusbok cool12:41
@juliusbI had come up with a patch (basically detecting that situation) but it got lost in my tree :-S12:42
@juliusbi committed it to my repo12:42
@juliusband I wasn't on a branch12:42
@juliusband now I can't find it again12:42
@stekernah, ok12:42
@juliusbso I had checked out a remote branch12:42
@juliusbbut not branched it locally12:42
@juliusband committed, and then it ust got lost when I branched away12:43
@juliusbit said I was in that (no branch) state or whatever12:43
@juliusbit wasn't massive change, but it sucks how git does that, and for git retards like me it can be scary haha12:43
@stekernI've seen some odd behaviour with ppc while reworking12:43
@stekerncould be related to that, but that could also be related to my rework12:44
@juliusbso my next set of work will involve setting up the versioning stuff correctly12:48
@juliusbi want to put the relevant bits in the architecture spec (update it according to what we discussed at ORCONF)12:48
@juliusband then put in the appropriate stuff to the mor1kx12:48
@juliusbhence the nice factoring of the cfgr SPRs12:48
@juliusbthat can be done easily12:48
@juliusbwell, relatively easily12:49
@juliusband then i'd like to release12:49
jonibojuliusb:  git reflog is your friend if you end up branching away from an unnamed head... it shows you all the commits that you've had at the HEAD of your tree, from most to least recent... it's just a matter of doing a 'git log <commit>' on all the commits in that list until you find your patch12:53
@juliusbahhh ok cool thanks jonibo !12:54
@olofkBeing sick sucks! I thought I would get loads of things done on orpsoc, but I'm just sleeping all the time :(15:01
LoneTechagreed. get well soon15:20
@olofkThanks LoneTech15:25
@juliusbhaha, yeah i know how you feel olofk , take it easy man, orpsoc will get done15:38
@stekernjuliusb (and olofk): I've been thinking about a different approach to the instruction tracing18:35
@stekernwhat about creating a (synthesizable) rtl module that is doing the snooping, that can then output the necessary information in a "binary format" that a parser can feed to or1ktrace18:37
@stekernthat'd be pretty cool, since then you could choose to do (small) traces in real hardware18:38
@stekernand log them to blockram and dump them18:38
@juliusboh yes, thatd be cool18:54
@juliusbcould also have things like l.nops loggable via that, too18:54
@juliusbit wouldn't be easy though18:55
@juliusbalthough, maybe it would18:55
@juliusbwhat i'm doing now is almost synthesisable (just using hierarchical references)18:55
@juliusbreplace the get-gpr function with something which knows what bus the outputted register value will be on18:56
-!- jeremy_bennett is now known as jeremybennett19:00
@stekernjuliusb: yeah, that's what got me started thinking along those lines, you've done most of the grunt work already ;)19:01
@stekernthe l.nops 8 and l.nops 9 I'd find extremely usable to be able to use on real hw19:01
@juliusbbut even the ability to sort of have a "debug" printing interface, like l.nop 0x2 but have that go to the trace output19:02
@juliusbthat would be bloody handy19:02
@juliusbyou'd just need to figure out a reasonably compact way of storing that in some block RAMs for dumping off later19:02
@juliusbbecause you'll potentially have (for a load/store op), 32-bits of binary plus 32-bits of calculated address plus 32-bits of data-bus result19:04
@juliusbbest case you just have 32-bits of binary for the instruction19:04
@juliusboh, PC too19:04
@juliusbso, best case is 64-bits of stuff per cycle19:04
@juliusbanyway, you may be doing up to 128-bits per cycle into a RAM, but most likely just 9619:05
@juliusbthen you need a way to get that off fast19:05
@juliusbor, is this just a logger, turn on and turn off19:05
@juliusbturn on and run until full maybe19:05
@juliusbyeah, that'd be a handy mode19:05
@juliusbthat'd be a fun project19:06
@juliusbif you have ethernet you could do somethign which is compatible with the OpenCores MAC and provides DMA to the buffer memory from the Wishbone bus19:10
@juliusbactually, that would be perfect19:10
@juliusbmake sure that memory is readable from the bus, then you could even dump it via GDB19:10
@juliusbor have something which adds on IP headers and sends it out to whatever IP you want19:11
@juliusbbut the simpler and still very useful solution is just some memory which you enable with a l.nop and dump to and can then be read via the debug interface later, or, even disassembled by the CPU itself and spat out to the screen19:13
@stekernexactly, I've had that kind of thing, logging signals and a wb-if and the cpu dumps it via uart19:17
@juliusbolofk: I've looked over the mor1kx-dev-env patch for the monitor trace file output, it all looks good19:40
@juliusbI'll apply it ASAP19:40
@olofkYeah, I'll been thinking about that kind of hardware tracing too. Dump to ethernet, pci, or whatever bus is available19:52
@olofkA bit of huffman or RLE would be nice too. I guess that could decrease the bandwidth quite a bit19:54
@juliusbya there's a lot of zeros in or1k instructions20:49
@juliusbit would be interesting to do a simple RLE encoding thing for zeroes on the or1k instructino set20:49
@juliusbwell, on or1k binary20:50
pgavinhey guys21:15
@olofkhi pgavin22:31
@juliusbpgavin: hey man!22:58
@juliusbbeen a while22:58
amsjuliusb: beer?23:31
@juliusbams: does the pope have a balcony?23:48
amsjuliusb: I wouldn't know, but I hope he has beer.23:49
* juliusb agrees23:49
ams(or at least red wine)23:49
amsSleep, cheers!23:49
@juliusblater mate23:49
@juliusbSo I'm finally sacrificing my development time to read up on some of this git stuff23:50
amsI'm trying to prioritise and see if I can do that gdb stuff...23:50
@juliusbAh no worries man, has anyone given you the steer to our port source?23:51
amsI uhm, don't remeber..23:51
amsI checked out some repo, or1k-src/gcc or something ..23:51
@juliusbMy git problem was that I keep checking out the remote branch (non-local branch) and not creating a local branch, then working on it, and the repo is then in detatched head state23:51
@juliusbah yes, the git one on
amsgit is a bit tricky ...23:52
amsYou reading one of the more fun pieces on git?23:52
@juliusbcool, if you want to nkow more about the gdb port (I believe pgavin had a bit of a port update under way but it hasn't seen the light day of yet, I could be wrong though)23:52
amsWill do!23:53
@juliusbthis is what has enlightened me:
amsNod.. i tend to use detached head's for lots of experimental stuff.23:54

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