| @olofk | I'm so fucking tired of crippled EDA tools. Has anyone been able to run Altera's modelsim version on 64 bit? I haven't figured out how to compile my VPI libs as 32 bit on my machine | 01:18 |
|---|---|---|
| @olofk | I guess I will need to learn how to cross-compile from 64 bit to 32 bit at some point anyway, soI might as well learn how to do that. Any clues? I've tried -m32 on gcc and ld without any great success | 01:22 |
| @olofk | Ha! -melf_i386 seems to have done the trick. That will have to do for now. | 01:23 |
| @olofk | Great. Modelsim with VPI works in orpsocv3 now. Still needs some cleaning up before any commits | 01:38 |
| _franck_ | stekern: if you have time, could you try the path I posted on the ml ? | 16:19 |
| _franck_ | I'm home this week and I can't wait to know how it works :) | 16:20 |
| _franck_ | +not | 16:21 |
| _franck_ | (I really have a problem forgetting words :)) | 16:22 |
| _franck_ | I meant *not* home | 16:22 |
| @juliusb | olofk: great news about the VPI stuff :) | 17:52 |
| @juliusb | stekern: at some point I had mor1kx-dev-env working with a binutils repo for trace in the cycle-accurate model, but I can't remember exactly how | 17:54 |
| @juliusb | it broke though at some point :( and I gave up | 17:54 |
| @juliusb | stekern: I might have some nice improvements for the mor1kx bus interface | 18:35 |
| @juliusb | that is, if you're running out of on-chip SRAM | 18:35 |
| @juliusb | we should be doing linear bursts | 18:36 |
| @juliusb | so we don't keep dropping the bus access line | 18:36 |
| @juliusb | I've been rewriting the fetch stage for the pronto espersso | 18:36 |
| @juliusb | espresso | 18:36 |
| @juliusb | so, without delay slot, you can immediately put out the address you're branching to on the next cycle | 18:37 |
| @juliusb | if you hooked it up to on-chip SRAM without a bus, you'd get very small branch latency | 18:37 |
| @juliusb | well, when I say without a bus, I mean without putting the access to the memory over a bus | 18:38 |
| @juliusb | it's not fully working yet, but I reckon we'd get some nice cache-less performance with the pronto espresso | 18:38 |
| @juliusb | seeing it stream in an exception vector 1 cycle at a time is quite nice | 18:39 |
| @juliusb | without breaks, right until the end | 18:39 |
| @juliusb | and even if you put a small cache on it, for loops or whatever, your branch penalty may only be 1 cycle if you're not doing a l.j[al]r | 18:42 |
| @juliusb | because all other branches you can basically tell as the instruction shows up on the input , where you're going to branch to | 18:43 |
| @juliusb | of course I havent synthesised this and I'm sure it's a load of logic on the end of the fetch data path which might slow things down, but as I said, if the memory is nice and close and doesn't go over the main bus, then it shouldn't be a problem | 18:45 |
| @juliusb | I doubt it's a problem even if you do go over a bus | 18:45 |
| -!- Netsplit *.net <-> *.split quits: orsoc1__ | 20:06 | |
| @stekern | _franck_: I will try to get around to it first thing in the morning ;) | 21:51 |
| @stekern | juliusb: cool | 21:51 |
| @stekern | if you're running out of onchip ram, there will of course be no point of having cache | 21:53 |
| @stekern | I need to get around to fixup cappuccino so it can run without icache | 21:54 |
| @stekern | and I'm eager to try out splitting up mem wb stages | 21:55 |
| @stekern | +and | 21:55 |
| @stekern | I seem to be suffering from same problem as _franck_, words fall out :) | 21:56 |
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