IRC logs for #openrisc Saturday, 2012-11-03

@olofkI'm so fucking tired of crippled EDA tools. Has anyone been able to run Altera's modelsim version on 64 bit? I haven't figured out how to compile my VPI libs as 32 bit on my machine01:18
@olofkI guess I will need to learn how to cross-compile from 64 bit to 32 bit at some point anyway, soI might as well learn how to do that. Any clues? I've tried -m32 on gcc and ld without any great success01:22
@olofkHa! -melf_i386 seems to have done the trick. That will have to do for now.01:23
@olofkGreat. Modelsim with VPI works in orpsocv3 now. Still needs some cleaning up before any commits01:38
_franck_stekern: if you have time, could you try the path I posted on the ml ?16:19
_franck_I'm home this week and I can't wait to know how it works :)16:20
_franck_(I really have a problem forgetting words :))16:22
_franck_I meant *not* home16:22
@juliusbolofk: great news about the VPI stuff :)17:52
@juliusbstekern: at some point I had mor1kx-dev-env working with a binutils repo for trace in the cycle-accurate model, but I can't remember exactly how17:54
@juliusbit broke though at some point :( and I gave up17:54
@juliusbstekern: I might have some nice improvements for the mor1kx bus interface18:35
@juliusbthat is, if you're running out of on-chip SRAM18:35
@juliusbwe should be doing linear bursts18:36
@juliusbso we don't keep dropping the bus access line18:36
@juliusbI've been rewriting the fetch stage for the pronto espersso18:36
@juliusbso, without delay slot, you can immediately put out the address you're branching to on the next cycle18:37
@juliusbif you hooked it up to on-chip SRAM without a bus, you'd get very small branch latency18:37
@juliusbwell, when I say without a bus, I mean without putting the access to the memory over a bus18:38
@juliusbit's not fully working yet, but I reckon we'd get some nice cache-less performance with the pronto espresso18:38
@juliusbseeing it stream in an exception vector 1 cycle at a time is quite nice18:39
@juliusbwithout breaks, right until the end18:39
@juliusband even if you put a small cache on it, for loops or whatever, your branch penalty may only be 1 cycle if you're not doing a l.j[al]r18:42
@juliusbbecause all other branches you can basically tell as the instruction shows up on the input , where you're going to branch to18:43
@juliusbof course I havent synthesised this and I'm sure it's a load of logic on the end of the fetch data path which might slow things down, but as I said, if the memory is nice and close and doesn't go over the main bus, then it shouldn't be a problem18:45
@juliusbI doubt it's a problem even if you do go over a bus18:45
-!- Netsplit *.net <-> *.split quits: orsoc1__20:06
@stekern_franck_: I will try to get around to it first thing in the morning ;)21:51
@stekernjuliusb: cool21:51
@stekernif you're running out of onchip ram, there will of course be no point of having cache21:53
@stekernI need to get around to fixup cappuccino so it can run without icache21:54
@stekernand I'm eager to try out splitting up mem wb stages21:55
@stekernI seem to be suffering from same problem as _franck_, words fall out :)21:56

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