IRC logs for #openrisc Friday, 2012-08-03

juliusbhmm, would an instruction where you jump with a register plus an immediate be of use?01:01
stekernjuliusb: I'm not sure but I have a feeling it could be useful for position independent code06:44
stekernjuliusb: (drop sfne) for fp, I don't think you can, since lf.sfeq;bf != lf.sfne;bnf06:47
stekernsince, (!qnan(a) && !qnan(b) && a == b) is not the same as  !(!qnan(a) && !qnan(b) && a != b)06:52
stekernalso, without it you will lose the ability to do not equal cmovs, i.e. r <= a != b ? x : y07:02
stekernscratch that last claim, I had clearly not woke up yet: r <= a != b ? x : y; can of course be transformed into r <= a == b ? y : x;09:14
juliusbstekern: how useful is cmov?12:35
juliusbat present I've not got it in my proposed ISA12:35
juliusbbut i very much like the idea12:35
juliusbcmov doesn't work like you proposed, though12:37
juliusbx = (a==b) ? y : x;12:37
juliusbisn't it?12:37
juliusbso you can only optionally write over a reg12:37
juliusbmaybe we do want some 3 reg version of cmov?12:37
stekernah well, you can transform it to y = (a==b) ? y : x then12:39
juliusbyes, but only if you have the ability to specify 3 registers12:40
juliusbi thought it was just cmov rA, rB12:40
juliusbwhere rA = (flag) ? rB : rA12:40
stekernx = (a!=b) ? x : y; => y = (a==b) ? x : y; then12:43
stekernI don't see any reason not having cmovs12:44
juliusbsure, a 3reg cmov12:46
juliusbi'd like to try and have it as a 16-bit insn12:46
stekernwhat is a 3reg?12:46
juliusb3 registers12:46
juliusbso you can specify rD, rA and rB12:47
juliusbas opposed to just rA and rB (where rD = rA)12:47
juliusbi think the existing one in or1k is the 2 register version12:47
stekernyes, that's of course nicer, but I don't know if it's strictly necessary12:47
juliusbi think it is if you only have sfeq12:47
juliusbbut... you know what I've done, we don't even have sfeq12:47
juliusbi'm considering putting it back in12:47
juliusbat present i just had sflt,sfgt,sfle,sfge12:48
stekernI have no idea what you've done ;)12:48
stekernx = (a!=b) ? x : y; => y = (a==b) ? x : y; <= doesn't that work?12:48
juliusbthen a jump-if-flag, jump-if-no-flag, but then jump-if-equal, jump-if-not-equal12:48
juliusbyou need a way of testing equality12:48
juliusbat present I don't have that12:49
stekernah, no sfeq even, yeah that might be a bit cheap :)12:49
juliusbbut im thinking of putting it back in and dropping the jump-if-eq12:49
juliusbbut jump-if-eq will be nice, because i have a 16-bit version which can skip over up to 8 insn12:49
stekernwhy do you continue with the flag stuff?12:50
juliusbbecause it's very nice to have the flag12:50
juliusband not put it in a register12:50
juliusbI mean a GPR12:50
juliusbyou get some bit of state for free12:50
stekernno, it's not nice12:50
juliusbbasically, 16-bit insns are too small to specify the comparison plus 2 regs plus put a useful immediate in it12:51
juliusbusing a state bit is beautiful, it saves you room in your jump/branch insn12:51
juliusbARM do it al ot12:51
juliusband I can see why, it really gives you a lot more room in your conditional insns12:52
juliusbso I thought, OK, for eq/ne then do it straight in the branch insn because you're likely to use those most12:52
juliusbso you save the sf then jump-if-flag duo and just have a single 16-bit insn12:52
juliusbi'll send you my scratchpad so fr12:53
juliusbso i've got a 6-bit opcode space12:57
juliusbso far i've used up to 0x38, meaning there's only 7 left12:58
juliusband I haven't got much in there12:58
stekernyeah, but arm have those nice predicated instructions...12:59
stekernwhat's bugging me most with the flag in or1k is that there isn't a nice way to get hold of the value of the flag without doing a branch13:02
juliusboh yeah13:02
stekern(especially not without a cmov)13:02
stekernso perhaps a cmov and cmovi to would be good to have if the flag-style is kept13:03
juliusbwhen do you want to know the flag value, though?13:04
juliusbhow often does that come up?13:04
stekernbetween 12:30 and 13:00 every thursday13:04
stekernnah, but we have discussed the cons with a flag earlier, one being that you only have one flag at your disposal, and if you don't have a way to "save-away" the flag other than branching, then you will be forced to branch (or at least do a branch decision) between every comparison13:13
stekernbut I see pro too, especially with as small immediate space13:16
juliusbim very tempted to just rip off the whole ARM many-flag-register13:17
juliusband have like a set-flag*s* insn13:18
juliusbthen we could have that in spr space and then just mfspr that register13:18
juliusbi was considering having a jump-if-bit-set insn, which worked on a value in a GPR13:21
juliusbor I guess, could work on a SPR13:21
juliusbso you do your set-flags, and then depending on which condition you want, select that bit13:21
juliusbbut could also be used to branch-if-lessthan-zero on a value without doing the compare (just test the top bit of the register, if it's '1' then it's <0 )13:22
juliusband maybe that's the best way, allow you do to the set-flags insn, and redirect the output to either a GPR or the SPR13:23
juliusband let the jump-if-bit-set insn select GPRs or the SPR13:23
juliusbGPRs or SPRs, even, perhaps13:23
stekernSPRs aren't really compilerfriendly though13:28
juliusbsure, could be useful for assembly function writing though13:29
stekernit's hard to get them grasp what is going on in them other than "it touches the SPR, so you have restrictions on what you can do with it"13:29
juliusbsure, but it'd still be easy enough to give it the concept of "this insn will be testing against bits in an SPR, which you don't have to worry your pretty little head about"13:32
stekernsure, but you have the problem that "this insn will modify bits in that SPR, so you better not do anything else that might modify it"13:33
stekernyou could probably model it per bit access though13:34
stekernwhat is the ARM many-flag-register called?13:34
juliusbyeah I think it's the CPSR: Current Program Status Register13:37
stekernI presume the three reg version for j(n)eq is for jump to reg?14:10
stekernwhat are the benefits of having seperate sts instructions?14:12
stekernjuliusb: wouldn't jnz rX, imm and jz rX, imm make more sense than jeq and jneq?14:32
stekernwe could have both of course14:32
stekernbtw, why are we aiming for a 32-bit _or_ 16-bit and not a mixed 16-bit/32-bit arch?14:47
stekernhmm, what is it that you have on sheet 1?14:51
stekernor1k cmov is 3reg btw15:40
juliusbI am aiming at mixed16:54
juliusbmixed is the way man, the only way :)16:54
juliusbget back to you other qs in a little while16:54
stekernyeah, I think _I_ got mixed up there for a while ;)17:31
stekernI was more thinking blackfin mixed though17:31
stekernonly instructions that don't need 32 bit space are 16-bit17:33
stekernI think I've got the fp comparisons worked out now at least (and with cmov as well)18:16
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