| stekern | question to toolchain gurus: how does insertion of global addresses at link-time work? | 07:25 |
|---|---|---|
| stekern | is a: l.movhi rX, hi(addr); l.ori rX, rX, lo(addr) sequence expected? | 07:26 |
| stekern | I've got a l.ori rX, r0, lo(addr) for a < 16-bit address, and when linking that with newlib it turns into l.ori r0, r0, lo(addr) | 07:27 |
| stekern | that a movhi, ori sequence will always be needed is pretty clear, my l.ori rX, r0 is a bug, but still, how does it work? | 07:32 |
| hjy | Hello | 12:36 |
| pgavin | juliusb: are you here? | 15:02 |
| hjy | What is the difference openrisc1000 and openrisc100? | 17:38 |
| hjy | openrisc1200 and openrisc1000 | 17:41 |
| pgavin | openrisc1000 (aka or1k) is a generic name for all machines in the architecture | 17:51 |
| pgavin | openrisc1200 is a specific implementation | 17:51 |
| hjy | opencores.org web site can't be opened! | 20:19 |
| hjy | Why? | 20:26 |
| gxti | works for me | 20:38 |
| juliusb | pgavin: here now | 22:37 |
| _franck_ | how could a binary behave differently with and without icache enable (the icache is invalidate at startup) ? | 23:56 |
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