| --- Log closed Wed Feb 08 01:35:09 2012 | ||
| --- Log opened Wed Feb 08 01:35:28 2012 | ||
| -!- Irssi: #openrisc: Total of 11 nicks [0 ops, 0 halfops, 0 voices, 11 normal] | 01:35 | |
| -!- Irssi: Join to #openrisc was synced in 45 secs | 01:36 | |
| -!- Netsplit *.net <-> *.split quits: orsoc1_ | 03:57 | |
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| -!- Netsplit *.net <-> *.split quits: olofk | 04:07 | |
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| -!- Netsplit *.net <-> *.split quits: derRichard | 04:12 | |
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| pgavin | hello | 14:29 |
|---|---|---|
| pgavin | anyone here? | 14:29 |
| jonibo | best to just ask your question and monitor for responses as they come | 14:30 |
| pgavin | kk | 14:30 |
| Blok | He just did :) Hello! | 14:30 |
| jonibo | "no" didn't seem an appropriate response, though... | 14:31 |
| pgavin | is there a gcc-4.6 tree anywhere that supports openrisc? :) | 14:31 |
| jonibo | no, not really | 14:31 |
| pgavin | k | 14:31 |
| jonibo | there's a couple of work in progress branches at git.openrisc.net | 14:31 |
| jonibo | but I'm not sure about the status of some of them | 14:32 |
| jonibo | giuseppe's gcc repo's are probably you're best bet | 14:32 |
| pgavin | ok | 14:32 |
| pgavin | thanks | 14:32 |
| jonibo | they should be 4.7 based | 14:32 |
| jonibo | (i think) | 14:32 |
| pgavin | what I want to do is modify the openrisc ISA to have no branch delay slot | 14:32 |
| pgavin | but I figured I'd start with the newest version of gcc | 14:32 |
| jonibo | ok, but branch delay slot is in the arch spec so it wouldn't be openrisc anymore | 14:33 |
| jonibo | aside from that... have fun! | 14:33 |
| pgavin | yeah, I know :) | 14:33 |
| pgavin | my professor wants a risc core with no delay slot lol | 14:33 |
| pgavin | it's complicated | 14:33 |
| jonibo | cool... I think it's a good idea, in general | 14:33 |
| pgavin | yeah, it's better when you have more developed pipelines | 14:33 |
| pgavin | but for a simple 5 stage it helps | 14:34 |
| pgavin | *helps to have a delay slot that is | 14:34 |
| pgavin | also, I found this: https://github.com/juliusbaxter/binutils-or1k | 14:34 |
| jonibo | yeah, he's working on the cgen integration | 14:35 |
| pgavin | does it work yet? | 14:35 |
| jonibo | i'd try to use that and help him along... | 14:35 |
| pgavin | ok | 14:35 |
| jonibo | I think it mostly works | 14:35 |
| pgavin | cool | 14:35 |
| pgavin | and will gcc recognize or1k as an arch name? | 14:35 |
| jonibo | no | 14:35 |
| pgavin | so I'll have to hack it a bit | 14:35 |
| jonibo | it's still or32 | 14:35 |
| pgavin | ok | 14:35 |
| pgavin | but that's no problem | 14:35 |
| jonibo | yup | 14:35 |
| pgavin | cool, thanks for the pointers | 14:37 |
| stekern | pgavin: sounds like a fun project, any chance the results will be published when you are done? | 14:53 |
| juliusb | pgavin: tell your professor to start work on openrisc 2000, but it would be trivial to change the GCC port I believe, the newlib port, not so much, and the linux kernel would need work ont he assembly bits | 15:10 |
| juliusb | regardingt he CGEN port - it looks like the binutils stuff works OK (still something up with relocations sometimes) and I have the simulator running basic stuff (hello worlds and the like) | 15:11 |
| juliusb | but, pgavin, your main problem will be with the RTL | 15:11 |
| juliusb | the fact that there's a delay slot is rather encrusted on a lot of the behavior of the OR1200 | 15:12 |
| pgavin | I want to publish them, yes :) | 15:13 |
| juliusb | so, to be honest, I wouldn't want to maintain 1) the binutils, GCC port 2) the simulator, 3) the RTL, 4) the software which doesn't have a delay slot | 15:13 |
| pgavin | yes, that's a lot to maintain | 15:13 |
| juliusb | in parallel with the rest of what's goin on | 15:13 |
| pgavin | the problem is that we've assumed no delay slot in our work | 15:14 |
| juliusb | it's a good idea to use OpenRISC, a bad one to want to fork the whole thing becuase you don't like delay slots | 15:14 |
| juliusb | what are you trying to do? you could force GCC to emit l.nops in every delay slot | 15:14 |
| pgavin | and we want to test it on a real core, but pretty much every core has a delay slot | 15:14 |
| pgavin | yeah, but the delay slots still pass through the pipeline | 15:14 |
| juliusb | yes | 15:14 |
| juliusb | but you always have a branch penalty anyway | 15:14 |
| pgavin | we've been using simplescalar, which uses an ISA like MIPS but without a delay slot | 15:15 |
| pgavin | and the only compiler that works with it is an absolutely ancient version of gcc | 15:15 |
| juliusb | :( | 15:15 |
| pgavin | our work involves branch prediction somewhat, and it makes little sense to have a predictor on a 5-stage pipeline with a delay slot | 15:16 |
| juliusb | that's right, pipeline's not long enough | 15:16 |
| pgavin | yeah, so basically, in order to show the effectiveness of what we've done, I want to make a core without a delay slot, and I'd figure I'd start with openrisc as the ISA | 15:17 |
| pgavin | I'm actually redoing the core because we need it structured differently than the openrisc core | 15:17 |
| juliusb | ok, that's fair enough, but as I said, to remove the delay slot you'll probably need to hack on a fair bit of stuff to get something compiling software and running it on an FPGA | 15:17 |
| pgavin | yeah, I expect to :) | 15:18 |
| pgavin | it won't be done in a week lol | 15:18 |
| juliusb | unfortunately no | 15:19 |
| pgavin | by the way, is this the best tree to use for the simulator? git://openrisc.net/julius/or1ksim | 15:20 |
| juliusb | no please use the or1ksim tree from the opencores.org site | 15:21 |
| juliusb | that's the mainline | 15:21 |
| pgavin | ok | 15:21 |
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