IRC logs for #openrisc Wednesday, 2012-02-08

--- Log closed Wed Feb 08 01:35:09 2012
--- Log opened Wed Feb 08 01:35:28 2012
-!- Irssi: #openrisc: Total of 11 nicks [0 ops, 0 halfops, 0 voices, 11 normal]01:35
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pgavinanyone here?14:29
jonibobest to just ask your question and monitor for responses as they come14:30
BlokHe just did :) Hello!14:30
jonibo"no" didn't seem an appropriate response, though...14:31
pgavinis there a gcc-4.6 tree anywhere that supports openrisc? :)14:31
jonibono, not really14:31
jonibothere's a couple of work in progress branches at git.openrisc.net14:31
jonibobut I'm not sure about the status of some of them14:32
jonibogiuseppe's gcc repo's are probably you're best bet14:32
jonibothey should be 4.7 based14:32
jonibo(i think)14:32
pgavinwhat I want to do is modify the openrisc ISA to have no branch delay slot14:32
pgavinbut I figured I'd start with the newest version of gcc14:32
jonibook, but branch delay slot is in the arch spec so it wouldn't be openrisc anymore14:33
joniboaside from that... have fun!14:33
pgavinyeah, I know :)14:33
pgavinmy professor wants a risc core with no delay slot lol14:33
pgavinit's complicated14:33
jonibocool... I think it's a good idea, in general14:33
pgavinyeah, it's better when you have more developed pipelines14:33
pgavinbut for a simple 5 stage it helps14:34
pgavin*helps to have a delay slot that is14:34
pgavinalso, I found this:
joniboyeah, he's working on the cgen integration14:35
pgavindoes it work yet?14:35
joniboi'd try to use that and help him along...14:35
joniboI think it mostly works14:35
pgavinand will gcc recognize or1k as an arch name?14:35
pgavinso I'll have to hack it a bit14:35
joniboit's still or3214:35
pgavinbut that's no problem14:35
pgavincool, thanks for the pointers14:37
stekernpgavin: sounds like a fun project, any chance the results will be published when you are done?14:53
juliusbpgavin: tell your professor to start work on openrisc 2000, but it would be trivial to change the GCC port I believe, the newlib port, not so much, and the linux kernel would need work ont he assembly bits15:10
juliusbregardingt he CGEN port - it looks like the binutils stuff works OK (still something up with relocations sometimes) and I have the simulator running basic stuff (hello worlds and the like)15:11
juliusbbut, pgavin, your main problem will be with the RTL15:11
juliusbthe fact that there's a delay slot is rather encrusted on a lot of the behavior of the OR120015:12
pgavinI want to publish them, yes :)15:13
juliusbso, to be honest, I wouldn't want to maintain 1) the binutils, GCC port 2) the simulator, 3) the RTL, 4) the software which doesn't have a delay slot15:13
pgavinyes, that's a lot to maintain15:13
juliusbin parallel with the rest of what's goin on15:13
pgavinthe problem is that we've assumed no delay slot in our work15:14
juliusbit's a good idea to use OpenRISC, a bad one to want to fork the whole thing becuase you don't like delay slots15:14
juliusbwhat are you trying to do? you could force GCC to emit l.nops in every delay slot15:14
pgavinand we want to test it on a real core, but pretty much every core has a delay slot15:14
pgavinyeah, but the delay slots still pass through the pipeline15:14
juliusbbut you always have a branch penalty anyway15:14
pgavinwe've been using simplescalar, which uses an ISA like MIPS but without a delay slot15:15
pgavinand the only compiler that works with it is an absolutely ancient version of gcc15:15
pgavinour work involves branch prediction somewhat, and it makes little sense to have a predictor on a 5-stage pipeline with a delay slot15:16
juliusbthat's right, pipeline's not long enough15:16
pgavinyeah, so basically, in order to show the effectiveness of what we've done, I want to make a core without a delay slot, and I'd figure I'd start with openrisc as the ISA15:17
pgavinI'm actually redoing the core because we need it structured differently than the openrisc core15:17
juliusbok, that's fair enough, but as I said, to remove the delay slot you'll probably need to hack on a fair bit of stuff to get something compiling software and running it on an FPGA15:17
pgavinyeah, I expect to :)15:18
pgavinit won't be done in a week lol15:18
juliusbunfortunately no15:19
pgavinby the way, is this the best tree to use for the simulator? git://
juliusbno please use the or1ksim tree from the site15:21
juliusbthat's the mainline15:21

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