A digital design engineer, from Australia, currently living and working in Cambridge, England.
Studied at the University of Queensland (BEng) and KTH, Stockholm (MSc).
IRC channel logs.
I work on the OpenRISC project where I develop CPU implementations and low-level software.
I host most of my current work at http://github.com/juliusbaxter (although, that's all pretty out of date, see the OpenRISC organisation on github for the most up to date stuff).
I also host logs for the #openrisc channel on irc.freenode.net.
Some other things are at OpenCores.orgI wrote my master's thesis on the project, you can download a PDF copy here.
I'm having a go at putting together a weak copyleft license for open source RTL designs.
A fork of the MPL2, the Open Hardware Description License (OHDL) aims to be more applicable to RTL code than software licenses, and make that code more likely to be used by industry. Find out more about it here.
Veripool.org - great open source Verilog and SystemC tools by the awesome Wilson Snyder
FuseSoC - the next-generation IP and SoC development environment
lowRISC - open source SoC
M-Labs - they actually make things
RISC-V - a worthy contemporary open source ISA
Cocotb - RTL testbenches in Python
PULP - One of the better RISC-V based multicore SoCs out there
ORCONF 2016, Bologna, Italy - Organiser
ORCONF 2015, Geneva, Switzerland - Organiser
ORCONF 2014, Munich, Germany - Organiser
EHSM #2, Hamburg, Germany - "The mor1kx OpenRISC processor" - video - EETimes article
Chip Hack May 2014, Cambridge, England - Tutorials on basic FPGA use and the OpenRISC Platform
ORCONF 2013, Cambridge, England - Organiser, workshop and "mor1kx progress report"
OHS2013, Boston, USA - "Open Chip Development: What there is to gain, and is it possible?"
Chip Hack April 2013, London, England - Tutorials on basic FPGA use and the OpenRISC Platform
ORCONF 2012 - Stockholm, Sweden - Organiser, and "The new mor1kx CPU core"
OSHUG 17, London, England - "Practical System-on-Chip (Program your own open source FPGA SoC)"
FSCONS 2012, Gothenburg, Sweden - "1576800000000000 cycles later (OpenRISC Project update)"
FOSDEM 2012, Brussels, Belgium - "True open hardware: Opencores and OpenRISC"
FSCONS 2011, Gothenburg, Sweden - "About The OpenRISC Project"
FSCONS 2011, Gothenburg, Sweden - "Workshop: The OpenRISC Project"
linux.conf.au 2011, Brisbane, Australia - "The OpenRISC Platform"
I also maintain this high-impact personal home page. I really should make this some kind of proper site some day...
juliusbaxter at gmail dot com
Find me in #openrisc on irc.freenode.net